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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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0a9375d129
The Tegra124 GPIO controller is identical to Tegra30, so copy the DT node from tegra30.dtsi to tegra124.dtsi. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
150 lines
3.7 KiB
Plaintext
150 lines
3.7 KiB
Plaintext
#include <dt-bindings/gpio/tegra-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra124";
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interrupt-parent = <&gic>;
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gic: interrupt-controller@50041000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x50041000 0x1000>,
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<0x50042000 0x1000>,
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<0x50044000 0x2000>,
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<0x50046000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer@60005000 {
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compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpio: gpio@6000d000 {
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compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
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reg = <0x6000d000 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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/*
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* There are two serial driver i.e. 8250 based simple serial
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* driver and APB DMA based serial driver for higher baudrate
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* and performace. To enable the 8250 based driver, the compatible
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* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
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* the APB DMA based serial driver, the comptible is
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* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
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*/
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serial@70006000 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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serial@70006040 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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serial@70006200 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006200 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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serial@70006300 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006300 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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serial@70006400 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006400 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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rtc@7000e000 {
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compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
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reg = <0x7000e000 0x100>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmc@7000e400 {
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compatible = "nvidia,tegra124-pmc";
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reg = <0x7000e400 0x400>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <3>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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