mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-27 05:30:56 +07:00
b1b3f49ce4
As suggested by Andrew Morton:
This is a pet peeve of mine. Any time there's a long list of items
(header file inclusions, kconfig entries, array initalisers, etc) and
someone wants to add a new item, they *always* go and stick it at the
end of the list.
Guys, don't do this. Either put the new item into a randomly-chosen
position or, probably better, alphanumerically sort the list.
lets sort all our select statements alphanumerically. This commit was
created by the following perl:
while (<>) {
while (/\\\s*$/) {
$_ .= <>;
}
undef %selects if /^\s*config\s+/;
if (/^\s+select\s+(\w+).*/) {
if (defined($selects{$1})) {
if ($selects{$1} eq $_) {
print STDERR "Warning: removing duplicated $1 entry\n";
} else {
print STDERR "Error: $1 differently selected\n".
"\tOld: $selects{$1}\n".
"\tNew: $_\n";
exit 1;
}
}
$selects{$1} = $_;
next;
}
if (%selects and (/^\s*$/ or /^\s+help/ or /^\s+---help---/ or
/^endif/ or /^endchoice/)) {
foreach $k (sort (keys %selects)) {
print "$selects{$k}";
}
undef %selects;
}
print;
}
if (%selects) {
foreach $k (sort (keys %selects)) {
print "$selects{$k}";
}
}
It found two duplicates:
Warning: removing duplicated S5P_SETUP_MIPIPHY entry
Warning: removing duplicated HARDIRQS_SW_RESEND entry
and they are identical duplicates, hence the shrinkage in the diffstat
of two lines.
We have four testers reporting success of this change (Tony, Stephen,
Linus and Sekhar.)
Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
894 lines
23 KiB
Plaintext
894 lines
23 KiB
Plaintext
comment "Processor Type"
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# Select CPU types depending on the architecture selected. This selects
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# which CPUs we support in the kernel image, and the compiler instruction
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# optimiser behaviour.
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# ARM7TDMI
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config CPU_ARM7TDMI
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bool "Support ARM7TDMI processor"
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depends on !MMU
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select CPU_32v4T
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select CPU_ABRT_LV4T
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select CPU_CACHE_V4
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select CPU_PABRT_LEGACY
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help
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A 32-bit RISC microprocessor based on the ARM7 processor core
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which has no memory control unit and cache.
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Say Y if you want support for the ARM7TDMI processor.
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Otherwise, say N.
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# ARM720T
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config CPU_ARM720T
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bool "Support ARM720T processor" if ARCH_INTEGRATOR
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select CPU_32v4T
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select CPU_ABRT_LV4T
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select CPU_CACHE_V4
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WT if MMU
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_V4WT if MMU
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help
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A 32-bit RISC processor with 8kByte Cache, Write Buffer and
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MMU built around an ARM7TDMI core.
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Say Y if you want support for the ARM720T processor.
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Otherwise, say N.
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# ARM740T
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config CPU_ARM740T
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bool "Support ARM740T processor" if ARCH_INTEGRATOR
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depends on !MMU
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select CPU_32v4T
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select CPU_ABRT_LV4T
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select CPU_CACHE_V3 # although the core is v4t
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select CPU_CP15_MPU
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select CPU_PABRT_LEGACY
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help
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A 32-bit RISC processor with 8KB cache or 4KB variants,
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write buffer and MPU(Protection Unit) built around
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an ARM7TDMI core.
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Say Y if you want support for the ARM740T processor.
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Otherwise, say N.
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# ARM9TDMI
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config CPU_ARM9TDMI
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bool "Support ARM9TDMI processor"
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depends on !MMU
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select CPU_32v4T
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select CPU_ABRT_NOMMU
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select CPU_CACHE_V4
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select CPU_PABRT_LEGACY
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help
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A 32-bit RISC microprocessor based on the ARM9 processor core
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which has no memory control unit and cache.
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Say Y if you want support for the ARM9TDMI processor.
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Otherwise, say N.
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# ARM920T
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config CPU_ARM920T
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bool "Support ARM920T processor" if ARCH_INTEGRATOR
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select CPU_32v4T
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB if MMU
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_V4WBI if MMU
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help
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The ARM920T is licensed to be produced by numerous vendors,
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and is used in the Cirrus EP93xx and the Samsung S3C2410.
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Say Y if you want support for the ARM920T processor.
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Otherwise, say N.
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# ARM922T
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config CPU_ARM922T
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bool "Support ARM922T processor" if ARCH_INTEGRATOR
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select CPU_32v4T
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB if MMU
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_V4WBI if MMU
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help
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The ARM922T is a version of the ARM920T, but with smaller
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instruction and data caches. It is used in Altera's
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Excalibur XA device family and Micrel's KS8695 Centaur.
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Say Y if you want support for the ARM922T processor.
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Otherwise, say N.
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# ARM925T
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config CPU_ARM925T
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bool "Support ARM925T processor" if ARCH_OMAP1
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select CPU_32v4T
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB if MMU
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_V4WBI if MMU
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help
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The ARM925T is a mix between the ARM920T and ARM926T, but with
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different instruction and data caches. It is used in TI's OMAP
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device family.
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Say Y if you want support for the ARM925T processor.
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Otherwise, say N.
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# ARM926T
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config CPU_ARM926T
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bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
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select CPU_32v5
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select CPU_ABRT_EV5TJ
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB if MMU
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_V4WBI if MMU
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help
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This is a variant of the ARM920. It has slightly different
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instruction sequences for cache and TLB operations. Curiously,
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there is no documentation on it at the ARM corporate website.
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Say Y if you want support for the ARM926T processor.
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Otherwise, say N.
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# FA526
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config CPU_FA526
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bool
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select CPU_32v4
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select CPU_ABRT_EV4
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select CPU_CACHE_FA
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select CPU_CACHE_VIVT
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select CPU_COPY_FA if MMU
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_FA if MMU
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help
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The FA526 is a version of the ARMv4 compatible processor with
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Branch Target Buffer, Unified TLB and cache line size 16.
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Say Y if you want support for the FA526 processor.
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Otherwise, say N.
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# ARM940T
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config CPU_ARM940T
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bool "Support ARM940T processor" if ARCH_INTEGRATOR
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depends on !MMU
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select CPU_32v4T
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select CPU_ABRT_NOMMU
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select CPU_CACHE_VIVT
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select CPU_CP15_MPU
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select CPU_PABRT_LEGACY
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help
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ARM940T is a member of the ARM9TDMI family of general-
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purpose microprocessors with MPU and separate 4KB
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instruction and 4KB data cases, each with a 4-word line
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length.
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Say Y if you want support for the ARM940T processor.
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Otherwise, say N.
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# ARM946E-S
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config CPU_ARM946E
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bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
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depends on !MMU
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select CPU_32v5
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select CPU_ABRT_NOMMU
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select CPU_CACHE_VIVT
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select CPU_CP15_MPU
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select CPU_PABRT_LEGACY
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help
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ARM946E-S is a member of the ARM9E-S family of high-
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performance, 32-bit system-on-chip processor solutions.
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The TCM and ARMv5TE 32-bit instruction set is supported.
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Say Y if you want support for the ARM946E-S processor.
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Otherwise, say N.
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# ARM1020 - needs validating
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config CPU_ARM1020
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bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB if MMU
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_V4WBI if MMU
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help
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The ARM1020 is the 32K cached version of the ARM10 processor,
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with an addition of a floating-point unit.
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Say Y if you want support for the ARM1020 processor.
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Otherwise, say N.
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# ARM1020E - needs validating
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config CPU_ARM1020E
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bool "Support ARM1020E processor" if ARCH_INTEGRATOR
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depends on n
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select CPU_32v5
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB if MMU
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_V4WBI if MMU
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# ARM1022E
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config CPU_ARM1022
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bool "Support ARM1022E processor" if ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV4T
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB if MMU # can probably do better
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_V4WBI if MMU
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help
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The ARM1022E is an implementation of the ARMv5TE architecture
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based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
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embedded trace macrocell, and a floating-point unit.
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Say Y if you want support for the ARM1022E processor.
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Otherwise, say N.
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# ARM1026EJ-S
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config CPU_ARM1026
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bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB if MMU # can probably do better
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_V4WBI if MMU
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help
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The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
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based upon the ARM10 integer core.
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Say Y if you want support for the ARM1026EJ-S processor.
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Otherwise, say N.
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# SA110
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config CPU_SA110
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bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
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select CPU_32v3 if ARCH_RPC
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select CPU_32v4 if !ARCH_RPC
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select CPU_ABRT_EV4
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select CPU_CACHE_V4WB
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB if MMU
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_V4WB if MMU
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help
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The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
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is available at five speeds ranging from 100 MHz to 233 MHz.
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More information is available at
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<http://developer.intel.com/design/strong/sa110.htm>.
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Say Y if you want support for the SA-110 processor.
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Otherwise, say N.
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# SA1100
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config CPU_SA1100
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bool
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select CPU_32v4
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select CPU_ABRT_EV4
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select CPU_CACHE_V4WB
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_V4WB if MMU
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# XScale
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config CPU_XSCALE
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bool
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select CPU_32v5
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select CPU_ABRT_EV5T
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_V4WBI if MMU
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# XScale Core Version 3
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config CPU_XSC3
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bool
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select CPU_32v5
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select CPU_ABRT_EV5T
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_V4WBI if MMU
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select IO_36
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# Marvell PJ1 (Mohawk)
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config CPU_MOHAWK
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bool
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select CPU_32v5
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select CPU_ABRT_EV5T
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB if MMU
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_V4WBI if MMU
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# Feroceon
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config CPU_FEROCEON
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bool
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select CPU_32v5
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select CPU_ABRT_EV5T
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select CPU_CACHE_VIVT
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select CPU_COPY_FEROCEON if MMU
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select CPU_CP15_MMU
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select CPU_PABRT_LEGACY
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select CPU_TLB_FEROCEON if MMU
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config CPU_FEROCEON_OLD_ID
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bool "Accept early Feroceon cores with an ARM926 ID"
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depends on CPU_FEROCEON && !CPU_ARM926T
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default y
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help
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This enables the usage of some old Feroceon cores
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for which the CPU ID is equal to the ARM926 ID.
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Relevant for Feroceon-1850 and early Feroceon-2850.
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# Marvell PJ4
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config CPU_PJ4
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bool
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select ARM_THUMBEE
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select CPU_V7
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# ARMv6
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config CPU_V6
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bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
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select CPU_32v6
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select CPU_ABRT_EV6
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select CPU_CACHE_V6
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select CPU_CACHE_VIPT
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select CPU_COPY_V6 if MMU
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select CPU_CP15_MMU
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select CPU_HAS_ASID if MMU
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select CPU_PABRT_V6
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select CPU_TLB_V6 if MMU
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# ARMv6k
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config CPU_V6K
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bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
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select CPU_32v6
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select CPU_32v6K
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select CPU_ABRT_EV6
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select CPU_CACHE_V6
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select CPU_CACHE_VIPT
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select CPU_COPY_V6 if MMU
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select CPU_CP15_MMU
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select CPU_HAS_ASID if MMU
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select CPU_PABRT_V6
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select CPU_TLB_V6 if MMU
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# ARMv7
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config CPU_V7
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bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
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select CPU_32v6K
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select CPU_32v7
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select CPU_ABRT_EV7
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select CPU_CACHE_V7
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select CPU_CACHE_VIPT
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select CPU_COPY_V6 if MMU
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select CPU_CP15_MMU
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select CPU_HAS_ASID if MMU
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select CPU_PABRT_V7
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select CPU_TLB_V7 if MMU
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# Figure out what processor architecture version we should be using.
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# This defines the compiler instruction set which depends on the machine type.
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config CPU_32v3
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bool
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select CPU_USE_DOMAINS if MMU
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select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
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select TLS_REG_EMUL if SMP || !MMU
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config CPU_32v4
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bool
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select CPU_USE_DOMAINS if MMU
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select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
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select TLS_REG_EMUL if SMP || !MMU
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config CPU_32v4T
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bool
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select CPU_USE_DOMAINS if MMU
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select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
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select TLS_REG_EMUL if SMP || !MMU
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config CPU_32v5
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bool
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select CPU_USE_DOMAINS if MMU
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select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
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select TLS_REG_EMUL if SMP || !MMU
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config CPU_32v6
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bool
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select CPU_USE_DOMAINS if CPU_V6 && MMU
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select TLS_REG_EMUL if !CPU_32v6K && !MMU
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config CPU_32v6K
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bool
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config CPU_32v7
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bool
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# The abort model
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config CPU_ABRT_NOMMU
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bool
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config CPU_ABRT_EV4
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bool
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config CPU_ABRT_EV4T
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bool
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config CPU_ABRT_LV4T
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bool
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config CPU_ABRT_EV5T
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bool
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config CPU_ABRT_EV5TJ
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bool
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config CPU_ABRT_EV6
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bool
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config CPU_ABRT_EV7
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bool
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config CPU_PABRT_LEGACY
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bool
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config CPU_PABRT_V6
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bool
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config CPU_PABRT_V7
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bool
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# The cache model
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config CPU_CACHE_V3
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bool
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config CPU_CACHE_V4
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bool
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config CPU_CACHE_V4WT
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bool
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config CPU_CACHE_V4WB
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bool
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config CPU_CACHE_V6
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bool
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config CPU_CACHE_V7
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bool
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config CPU_CACHE_VIVT
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bool
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|
|
config CPU_CACHE_VIPT
|
|
bool
|
|
|
|
config CPU_CACHE_FA
|
|
bool
|
|
|
|
if MMU
|
|
# The copy-page model
|
|
config CPU_COPY_V4WT
|
|
bool
|
|
|
|
config CPU_COPY_V4WB
|
|
bool
|
|
|
|
config CPU_COPY_FEROCEON
|
|
bool
|
|
|
|
config CPU_COPY_FA
|
|
bool
|
|
|
|
config CPU_COPY_V6
|
|
bool
|
|
|
|
# This selects the TLB model
|
|
config CPU_TLB_V4WT
|
|
bool
|
|
help
|
|
ARM Architecture Version 4 TLB with writethrough cache.
|
|
|
|
config CPU_TLB_V4WB
|
|
bool
|
|
help
|
|
ARM Architecture Version 4 TLB with writeback cache.
|
|
|
|
config CPU_TLB_V4WBI
|
|
bool
|
|
help
|
|
ARM Architecture Version 4 TLB with writeback cache and invalidate
|
|
instruction cache entry.
|
|
|
|
config CPU_TLB_FEROCEON
|
|
bool
|
|
help
|
|
Feroceon TLB (v4wbi with non-outer-cachable page table walks).
|
|
|
|
config CPU_TLB_FA
|
|
bool
|
|
help
|
|
Faraday ARM FA526 architecture, unified TLB with writeback cache
|
|
and invalidate instruction cache entry. Branch target buffer is
|
|
also supported.
|
|
|
|
config CPU_TLB_V6
|
|
bool
|
|
|
|
config CPU_TLB_V7
|
|
bool
|
|
|
|
config VERIFY_PERMISSION_FAULT
|
|
bool
|
|
endif
|
|
|
|
config CPU_HAS_ASID
|
|
bool
|
|
help
|
|
This indicates whether the CPU has the ASID register; used to
|
|
tag TLB and possibly cache entries.
|
|
|
|
config CPU_CP15
|
|
bool
|
|
help
|
|
Processor has the CP15 register.
|
|
|
|
config CPU_CP15_MMU
|
|
bool
|
|
select CPU_CP15
|
|
help
|
|
Processor has the CP15 register, which has MMU related registers.
|
|
|
|
config CPU_CP15_MPU
|
|
bool
|
|
select CPU_CP15
|
|
help
|
|
Processor has the CP15 register, which has MPU related registers.
|
|
|
|
config CPU_USE_DOMAINS
|
|
bool
|
|
help
|
|
This option enables or disables the use of domain switching
|
|
via the set_fs() function.
|
|
|
|
#
|
|
# CPU supports 36-bit I/O
|
|
#
|
|
config IO_36
|
|
bool
|
|
|
|
comment "Processor Features"
|
|
|
|
config ARM_LPAE
|
|
bool "Support for the Large Physical Address Extension"
|
|
depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
|
|
!CPU_32v4 && !CPU_32v3
|
|
help
|
|
Say Y if you have an ARMv7 processor supporting the LPAE page
|
|
table format and you would like to access memory beyond the
|
|
4GB limit. The resulting kernel image will not run on
|
|
processors without the LPA extension.
|
|
|
|
If unsure, say N.
|
|
|
|
config ARCH_PHYS_ADDR_T_64BIT
|
|
def_bool ARM_LPAE
|
|
|
|
config ARCH_DMA_ADDR_T_64BIT
|
|
bool
|
|
|
|
config ARM_THUMB
|
|
bool "Support Thumb user binaries"
|
|
depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
|
|
default y
|
|
help
|
|
Say Y if you want to include kernel support for running user space
|
|
Thumb binaries.
|
|
|
|
The Thumb instruction set is a compressed form of the standard ARM
|
|
instruction set resulting in smaller binaries at the expense of
|
|
slightly less efficient code.
|
|
|
|
If you don't know what this all is, saying Y is a safe choice.
|
|
|
|
config ARM_THUMBEE
|
|
bool "Enable ThumbEE CPU extension"
|
|
depends on CPU_V7
|
|
help
|
|
Say Y here if you have a CPU with the ThumbEE extension and code to
|
|
make use of it. Say N for code that can run on CPUs without ThumbEE.
|
|
|
|
config ARM_VIRT_EXT
|
|
bool "Native support for the ARM Virtualization Extensions"
|
|
depends on MMU && CPU_V7
|
|
help
|
|
Enable the kernel to make use of the ARM Virtualization
|
|
Extensions to install hypervisors without run-time firmware
|
|
assistance.
|
|
|
|
A compliant bootloader is required in order to make maximum
|
|
use of this feature. Refer to Documentation/arm/Booting for
|
|
details.
|
|
|
|
It is safe to enable this option even if the kernel may not be
|
|
booted in HYP mode, may not have support for the
|
|
virtualization extensions, or may be booted with a
|
|
non-compliant bootloader.
|
|
|
|
config SWP_EMULATE
|
|
bool "Emulate SWP/SWPB instructions"
|
|
depends on !CPU_USE_DOMAINS && CPU_V7
|
|
default y if SMP
|
|
select HAVE_PROC_CPU if PROC_FS
|
|
help
|
|
ARMv6 architecture deprecates use of the SWP/SWPB instructions.
|
|
ARMv7 multiprocessing extensions introduce the ability to disable
|
|
these instructions, triggering an undefined instruction exception
|
|
when executed. Say Y here to enable software emulation of these
|
|
instructions for userspace (not kernel) using LDREX/STREX.
|
|
Also creates /proc/cpu/swp_emulation for statistics.
|
|
|
|
In some older versions of glibc [<=2.8] SWP is used during futex
|
|
trylock() operations with the assumption that the code will not
|
|
be preempted. This invalid assumption may be more likely to fail
|
|
with SWP emulation enabled, leading to deadlock of the user
|
|
application.
|
|
|
|
NOTE: when accessing uncached shared regions, LDREX/STREX rely
|
|
on an external transaction monitoring block called a global
|
|
monitor to maintain update atomicity. If your system does not
|
|
implement a global monitor, this option can cause programs that
|
|
perform SWP operations to uncached memory to deadlock.
|
|
|
|
If unsure, say Y.
|
|
|
|
config CPU_BIG_ENDIAN
|
|
bool "Build big-endian kernel"
|
|
depends on ARCH_SUPPORTS_BIG_ENDIAN
|
|
help
|
|
Say Y if you plan on running a kernel in big-endian mode.
|
|
Note that your board must be properly built and your board
|
|
port must properly enable any big-endian related features
|
|
of your chipset/board/processor.
|
|
|
|
config CPU_ENDIAN_BE8
|
|
bool
|
|
depends on CPU_BIG_ENDIAN
|
|
default CPU_V6 || CPU_V6K || CPU_V7
|
|
help
|
|
Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
|
|
|
|
config CPU_ENDIAN_BE32
|
|
bool
|
|
depends on CPU_BIG_ENDIAN
|
|
default !CPU_ENDIAN_BE8
|
|
help
|
|
Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
|
|
|
|
config CPU_HIGH_VECTOR
|
|
depends on !MMU && CPU_CP15 && !CPU_ARM740T
|
|
bool "Select the High exception vector"
|
|
help
|
|
Say Y here to select high exception vector(0xFFFF0000~).
|
|
The exception vector can vary depending on the platform
|
|
design in nommu mode. If your platform needs to select
|
|
high exception vector, say Y.
|
|
Otherwise or if you are unsure, say N, and the low exception
|
|
vector (0x00000000~) will be used.
|
|
|
|
config CPU_ICACHE_DISABLE
|
|
bool "Disable I-Cache (I-bit)"
|
|
depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
|
|
help
|
|
Say Y here to disable the processor instruction cache. Unless
|
|
you have a reason not to or are unsure, say N.
|
|
|
|
config CPU_DCACHE_DISABLE
|
|
bool "Disable D-Cache (C-bit)"
|
|
depends on CPU_CP15
|
|
help
|
|
Say Y here to disable the processor data cache. Unless
|
|
you have a reason not to or are unsure, say N.
|
|
|
|
config CPU_DCACHE_SIZE
|
|
hex
|
|
depends on CPU_ARM740T || CPU_ARM946E
|
|
default 0x00001000 if CPU_ARM740T
|
|
default 0x00002000 # default size for ARM946E-S
|
|
help
|
|
Some cores are synthesizable to have various sized cache. For
|
|
ARM946E-S case, it can vary from 0KB to 1MB.
|
|
To support such cache operations, it is efficient to know the size
|
|
before compile time.
|
|
If your SoC is configured to have a different size, define the value
|
|
here with proper conditions.
|
|
|
|
config CPU_DCACHE_WRITETHROUGH
|
|
bool "Force write through D-cache"
|
|
depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
|
|
default y if CPU_ARM925T
|
|
help
|
|
Say Y here to use the data cache in writethrough mode. Unless you
|
|
specifically require this or are unsure, say N.
|
|
|
|
config CPU_CACHE_ROUND_ROBIN
|
|
bool "Round robin I and D cache replacement algorithm"
|
|
depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
|
|
help
|
|
Say Y here to use the predictable round-robin cache replacement
|
|
policy. Unless you specifically require this or are unsure, say N.
|
|
|
|
config CPU_BPREDICT_DISABLE
|
|
bool "Disable branch prediction"
|
|
depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
|
|
help
|
|
Say Y here to disable branch prediction. If unsure, say N.
|
|
|
|
config TLS_REG_EMUL
|
|
bool
|
|
help
|
|
An SMP system using a pre-ARMv6 processor (there are apparently
|
|
a few prototypes like that in existence) and therefore access to
|
|
that required register must be emulated.
|
|
|
|
config NEEDS_SYSCALL_FOR_CMPXCHG
|
|
bool
|
|
help
|
|
SMP on a pre-ARMv6 processor? Well OK then.
|
|
Forget about fast user space cmpxchg support.
|
|
It is just not possible.
|
|
|
|
config DMA_CACHE_RWFO
|
|
bool "Enable read/write for ownership DMA cache maintenance"
|
|
depends on CPU_V6K && SMP
|
|
default y
|
|
help
|
|
The Snoop Control Unit on ARM11MPCore does not detect the
|
|
cache maintenance operations and the dma_{map,unmap}_area()
|
|
functions may leave stale cache entries on other CPUs. By
|
|
enabling this option, Read or Write For Ownership in the ARMv6
|
|
DMA cache maintenance functions is performed. These LDR/STR
|
|
instructions change the cache line state to shared or modified
|
|
so that the cache operation has the desired effect.
|
|
|
|
Note that the workaround is only valid on processors that do
|
|
not perform speculative loads into the D-cache. For such
|
|
processors, if cache maintenance operations are not broadcast
|
|
in hardware, other workarounds are needed (e.g. cache
|
|
maintenance broadcasting in software via FIQ).
|
|
|
|
config OUTER_CACHE
|
|
bool
|
|
|
|
config OUTER_CACHE_SYNC
|
|
bool
|
|
help
|
|
The outer cache has a outer_cache_fns.sync function pointer
|
|
that can be used to drain the write buffer of the outer cache.
|
|
|
|
config CACHE_FEROCEON_L2
|
|
bool "Enable the Feroceon L2 cache controller"
|
|
depends on ARCH_KIRKWOOD || ARCH_MV78XX0
|
|
default y
|
|
select OUTER_CACHE
|
|
help
|
|
This option enables the Feroceon L2 cache controller.
|
|
|
|
config CACHE_FEROCEON_L2_WRITETHROUGH
|
|
bool "Force Feroceon L2 cache write through"
|
|
depends on CACHE_FEROCEON_L2
|
|
help
|
|
Say Y here to use the Feroceon L2 cache in writethrough mode.
|
|
Unless you specifically require this, say N for writeback mode.
|
|
|
|
config MIGHT_HAVE_CACHE_L2X0
|
|
bool
|
|
help
|
|
This option should be selected by machines which have a L2x0
|
|
or PL310 cache controller, but where its use is optional.
|
|
|
|
The only effect of this option is to make CACHE_L2X0 and
|
|
related options available to the user for configuration.
|
|
|
|
Boards or SoCs which always require the cache controller
|
|
support to be present should select CACHE_L2X0 directly
|
|
instead of this option, thus preventing the user from
|
|
inadvertently configuring a broken kernel.
|
|
|
|
config CACHE_L2X0
|
|
bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
|
|
default MIGHT_HAVE_CACHE_L2X0
|
|
select OUTER_CACHE
|
|
select OUTER_CACHE_SYNC
|
|
help
|
|
This option enables the L2x0 PrimeCell.
|
|
|
|
config CACHE_PL310
|
|
bool
|
|
depends on CACHE_L2X0
|
|
default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
|
|
help
|
|
This option enables optimisations for the PL310 cache
|
|
controller.
|
|
|
|
config CACHE_TAUROS2
|
|
bool "Enable the Tauros2 L2 cache controller"
|
|
depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
|
|
default y
|
|
select OUTER_CACHE
|
|
help
|
|
This option enables the Tauros2 L2 cache controller (as
|
|
found on PJ1/PJ4).
|
|
|
|
config CACHE_XSC3L2
|
|
bool "Enable the L2 cache on XScale3"
|
|
depends on CPU_XSC3
|
|
default y
|
|
select OUTER_CACHE
|
|
help
|
|
This option enables the L2 cache on XScale3.
|
|
|
|
config ARM_L1_CACHE_SHIFT_6
|
|
bool
|
|
default y if CPU_V7
|
|
help
|
|
Setting ARM L1 cache line size to 64 Bytes.
|
|
|
|
config ARM_L1_CACHE_SHIFT
|
|
int
|
|
default 6 if ARM_L1_CACHE_SHIFT_6
|
|
default 5
|
|
|
|
config ARM_DMA_MEM_BUFFERABLE
|
|
bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
|
|
depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
|
|
MACH_REALVIEW_PB11MP)
|
|
default y if CPU_V6 || CPU_V6K || CPU_V7
|
|
help
|
|
Historically, the kernel has used strongly ordered mappings to
|
|
provide DMA coherent memory. With the advent of ARMv7, mapping
|
|
memory with differing types results in unpredictable behaviour,
|
|
so on these CPUs, this option is forced on.
|
|
|
|
Multiple mappings with differing attributes is also unpredictable
|
|
on ARMv6 CPUs, but since they do not have aggressive speculative
|
|
prefetch, no harm appears to occur.
|
|
|
|
However, drivers may be missing the necessary barriers for ARMv6,
|
|
and therefore turning this on may result in unpredictable driver
|
|
behaviour. Therefore, we offer this as an option.
|
|
|
|
You are recommended say 'Y' here and debug any affected drivers.
|
|
|
|
config ARCH_HAS_BARRIERS
|
|
bool
|
|
help
|
|
This option allows the use of custom mandatory barriers
|
|
included via the mach/barriers.h file.
|