mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
a9f2fc628e
Make kernel load address explicit, independent of the selected MMU configuration and configurable from Kconfig. Do not restrict it to the first 512MB of the physical address space. Cleanup kernel memory layout macros: - rename VECBASE_RESET_VADDR to VECBASE_VADDR, XC_VADDR to VECTOR_VADDR; - drop VIRTUAL_MEMORY_ADDRESS and LOAD_MEMORY_ADDRESS; - introduce PHYS_OFFSET and use it in __va and __pa definitions; - synchronize MMU/noMMU vectors, drop unused NMI vector; - replace hardcoded vectors offset of 0x3000 with Kconfig symbol. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
80 lines
1.5 KiB
ArmAsm
80 lines
1.5 KiB
ArmAsm
/*
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* arch/xtensa/boot/boot-elf/bootstrap.S
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*
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* Low-level exception handling
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004 - 2013 by Tensilica Inc.
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*
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* Chris Zankel <chris@zankel.net>
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* Marc Gauthier <marc@tensilica.com>
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* Piet Delaney <piet@tensilica.com>
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*/
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#include <asm/bootparam.h>
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#include <asm/processor.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/cacheasm.h>
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#include <asm/initialize_mmu.h>
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#include <asm/vectors.h>
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#include <linux/linkage.h>
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.section .ResetVector.text, "ax"
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.global _ResetVector
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.global reset
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_ResetVector:
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_j _SetupMMU
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.begin no-absolute-literals
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.literal_position
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.align 4
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RomInitAddr:
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#if defined(CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) && \
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XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
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.word CONFIG_KERNEL_LOAD_ADDRESS
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#else
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.word KERNELOFFSET
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#endif
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RomBootParam:
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.word _bootparam
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_bootparam:
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.short BP_TAG_FIRST
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.short 4
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.long BP_VERSION
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.short BP_TAG_LAST
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.short 0
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.long 0
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.align 4
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_SetupMMU:
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movi a0, 0
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wsr a0, windowbase
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rsync
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movi a0, 1
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wsr a0, windowstart
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rsync
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movi a0, 0x1F
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wsr a0, ps
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rsync
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#ifndef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
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initialize_mmu
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#endif
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.end no-absolute-literals
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rsil a0, XCHAL_DEBUGLEVEL-1
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rsync
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reset:
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l32r a0, RomInitAddr
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l32r a2, RomBootParam
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movi a3, 0
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movi a4, 0
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jx a0
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