mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
605add0c7b
The RCC block is responsible of the management of the clock and reset generation for the complete circuit. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
61 lines
2.0 KiB
Plaintext
61 lines
2.0 KiB
Plaintext
STMicroelectronics STM32 Peripheral Reset Clock Controller
|
|
==========================================================
|
|
|
|
The RCC IP is both a reset and a clock controller.
|
|
|
|
RCC makes also power management (resume/supend and wakeup interrupt).
|
|
|
|
Please also refer to reset.txt for common reset controller binding usage.
|
|
|
|
Please also refer to clock-bindings.txt for common clock controller
|
|
binding usage.
|
|
|
|
|
|
Required properties:
|
|
- compatible: "st,stm32mp1-rcc", "syscon"
|
|
- reg: should be register base and length as documented in the datasheet
|
|
- #clock-cells: 1, device nodes should specify the clock in their
|
|
"clocks" property, containing a phandle to the clock device node,
|
|
an index specifying the clock to use.
|
|
- #reset-cells: Shall be 1
|
|
- interrupts: Should contain a general interrupt line and a interrupt line
|
|
to the wake-up of processor (CSTOP).
|
|
|
|
Example:
|
|
rcc: rcc@50000000 {
|
|
compatible = "st,stm32mp1-rcc", "syscon";
|
|
reg = <0x50000000 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>,
|
|
<GIC_SPI 145 IRQ_TYPE_NONE>;
|
|
};
|
|
|
|
Specifying clocks
|
|
=================
|
|
|
|
All available clocks are defined as preprocessor macros in
|
|
dt-bindings/clock/stm32mp1-clks.h header and can be used in device
|
|
tree sources.
|
|
|
|
Specifying softreset control of devices
|
|
=======================================
|
|
|
|
Device nodes should specify the reset channel required in their "resets"
|
|
property, containing a phandle to the reset device node and an index specifying
|
|
which channel to use.
|
|
The index is the bit number within the RCC registers bank, starting from RCC
|
|
base address.
|
|
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
|
|
Where bit_offset is the bit offset within the register.
|
|
|
|
For example on STM32MP1, for LTDC reset:
|
|
ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
|
|
= 0x180 / 4 * 32 + 0 = 3072
|
|
|
|
The list of valid indices for STM32MP1 is available in:
|
|
include/dt-bindings/reset-controller/stm32mp1-resets.h
|
|
|
|
This file implements defines like:
|
|
#define LTDC_R 3072
|