linux_dsm_epyc7002/drivers/gpu/drm/i915/selftests/igt_reset.c
Michal Wajdeczko f6470c9bcc drm/i915/selftests: Split igt_atomic_reset testcase
Split igt_atomic_reset selftests into separate full & engines parts,
so we can move former to the dedicated reset selftests file.

While here change engines test to loop first over atomic phases and
then loop over available engines.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190522193203.23932-3-michal.wajdeczko@intel.com
2019-05-23 21:53:26 +01:00

54 lines
1.2 KiB
C

/*
* SPDX-License-Identifier: MIT
*
* Copyright © 2018 Intel Corporation
*/
#include "igt_reset.h"
#include "gt/intel_engine.h"
#include "../i915_drv.h"
void igt_global_reset_lock(struct drm_i915_private *i915)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
pr_debug("%s: current gpu_error=%08lx\n",
__func__, i915->gpu_error.flags);
while (test_and_set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags))
wait_event(i915->gpu_error.reset_queue,
!test_bit(I915_RESET_BACKOFF,
&i915->gpu_error.flags));
for_each_engine(engine, i915, id) {
while (test_and_set_bit(I915_RESET_ENGINE + id,
&i915->gpu_error.flags))
wait_on_bit(&i915->gpu_error.flags,
I915_RESET_ENGINE + id,
TASK_UNINTERRUPTIBLE);
}
}
void igt_global_reset_unlock(struct drm_i915_private *i915)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
for_each_engine(engine, i915, id)
clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags);
wake_up_all(&i915->gpu_error.reset_queue);
}
bool igt_force_reset(struct drm_i915_private *i915)
{
i915_gem_set_wedged(i915);
i915_reset(i915, 0, NULL);
return !i915_reset_failed(i915);
}