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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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57d7cdb630
Add IRT to IRQ translation for the MMC and I2C IRQs. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3761/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
164 lines
4.8 KiB
C
164 lines
4.8 KiB
C
/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <asm/mipsregs.h>
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#include <asm/time.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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#include <asm/netlogic/xlp-hal/sys.h>
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/* These addresses are computed by the nlm_hal_init() */
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uint64_t nlm_io_base;
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uint64_t nlm_sys_base;
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uint64_t nlm_pic_base;
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/* Main initialization */
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void nlm_hal_init(void)
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{
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nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
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nlm_sys_base = nlm_get_sys_regbase(0); /* node 0 */
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nlm_pic_base = nlm_get_pic_regbase(0); /* node 0 */
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}
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int nlm_irq_to_irt(int irq)
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{
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if (!PIC_IRQ_IS_IRT(irq))
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return -1;
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switch (irq) {
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case PIC_UART_0_IRQ:
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return PIC_IRT_UART_0_INDEX;
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case PIC_UART_1_IRQ:
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return PIC_IRT_UART_1_INDEX;
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case PIC_PCIE_LINK_0_IRQ:
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return PIC_IRT_PCIE_LINK_0_INDEX;
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case PIC_PCIE_LINK_1_IRQ:
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return PIC_IRT_PCIE_LINK_1_INDEX;
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case PIC_PCIE_LINK_2_IRQ:
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return PIC_IRT_PCIE_LINK_2_INDEX;
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case PIC_PCIE_LINK_3_IRQ:
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return PIC_IRT_PCIE_LINK_3_INDEX;
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case PIC_EHCI_0_IRQ:
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return PIC_IRT_EHCI_0_INDEX;
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case PIC_EHCI_1_IRQ:
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return PIC_IRT_EHCI_1_INDEX;
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case PIC_OHCI_0_IRQ:
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return PIC_IRT_OHCI_0_INDEX;
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case PIC_OHCI_1_IRQ:
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return PIC_IRT_OHCI_1_INDEX;
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case PIC_OHCI_2_IRQ:
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return PIC_IRT_OHCI_2_INDEX;
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case PIC_OHCI_3_IRQ:
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return PIC_IRT_OHCI_3_INDEX;
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case PIC_MMC_IRQ:
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return PIC_IRT_MMC_INDEX;
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case PIC_I2C_0_IRQ:
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return PIC_IRT_I2C_0_INDEX;
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case PIC_I2C_1_IRQ:
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return PIC_IRT_I2C_1_INDEX;
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default:
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return -1;
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}
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}
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int nlm_irt_to_irq(int irt)
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{
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switch (irt) {
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case PIC_IRT_UART_0_INDEX:
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return PIC_UART_0_IRQ;
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case PIC_IRT_UART_1_INDEX:
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return PIC_UART_1_IRQ;
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case PIC_IRT_PCIE_LINK_0_INDEX:
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return PIC_PCIE_LINK_0_IRQ;
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case PIC_IRT_PCIE_LINK_1_INDEX:
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return PIC_PCIE_LINK_1_IRQ;
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case PIC_IRT_PCIE_LINK_2_INDEX:
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return PIC_PCIE_LINK_2_IRQ;
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case PIC_IRT_PCIE_LINK_3_INDEX:
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return PIC_PCIE_LINK_3_IRQ;
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case PIC_IRT_EHCI_0_INDEX:
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return PIC_EHCI_0_IRQ;
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case PIC_IRT_EHCI_1_INDEX:
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return PIC_EHCI_1_IRQ;
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case PIC_IRT_OHCI_0_INDEX:
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return PIC_OHCI_0_IRQ;
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case PIC_IRT_OHCI_1_INDEX:
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return PIC_OHCI_1_IRQ;
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case PIC_IRT_OHCI_2_INDEX:
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return PIC_OHCI_2_IRQ;
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case PIC_IRT_OHCI_3_INDEX:
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return PIC_OHCI_3_IRQ;
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case PIC_IRT_MMC_INDEX:
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return PIC_MMC_IRQ;
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case PIC_IRT_I2C_0_INDEX:
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return PIC_I2C_0_IRQ;
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case PIC_IRT_I2C_1_INDEX:
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return PIC_I2C_1_IRQ;
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default:
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return -1;
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}
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}
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unsigned int nlm_get_core_frequency(int core)
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{
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unsigned int pll_divf, pll_divr, dfs_div, ext_div;
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unsigned int rstval, dfsval, denom;
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uint64_t num;
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rstval = nlm_read_sys_reg(nlm_sys_base, SYS_POWER_ON_RESET_CFG);
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dfsval = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIV_VALUE);
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pll_divf = ((rstval >> 10) & 0x7f) + 1;
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pll_divr = ((rstval >> 8) & 0x3) + 1;
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ext_div = ((rstval >> 30) & 0x3) + 1;
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dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
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num = 800000000ULL * pll_divf;
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denom = 3 * pll_divr * ext_div * dfs_div;
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do_div(num, denom);
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return (unsigned int)num;
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}
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unsigned int nlm_get_cpu_frequency(void)
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{
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return nlm_get_core_frequency(0);
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}
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