mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 21:16:51 +07:00
f0cfffc48c
MMU-500 erratum #841119 is tickled by a particular set of circumstances interacting with the next-page prefetcher. Since said prefetcher is quite dumb and actually detrimental to performance in some cases (by causing unwanted TLB evictions for non-sequential access patterns), we lose very little by turning it off, and what we gain is a guarantee that the erratum is never hit. As a bonus, the same workaround will also prevent erratum #826419 once v7 short descriptor support is implemented. CC: Catalin Marinas <catalin.marinas@arm.com> CC: Will Deacon <will.deacon@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
62 lines
3.4 KiB
Plaintext
62 lines
3.4 KiB
Plaintext
Silicon Errata and Software Workarounds
|
|
=======================================
|
|
|
|
Author: Will Deacon <will.deacon@arm.com>
|
|
Date : 27 November 2015
|
|
|
|
It is an unfortunate fact of life that hardware is often produced with
|
|
so-called "errata", which can cause it to deviate from the architecture
|
|
under specific circumstances. For hardware produced by ARM, these
|
|
errata are broadly classified into the following categories:
|
|
|
|
Category A: A critical error without a viable workaround.
|
|
Category B: A significant or critical error with an acceptable
|
|
workaround.
|
|
Category C: A minor error that is not expected to occur under normal
|
|
operation.
|
|
|
|
For more information, consult one of the "Software Developers Errata
|
|
Notice" documents available on infocenter.arm.com (registration
|
|
required).
|
|
|
|
As far as Linux is concerned, Category B errata may require some special
|
|
treatment in the operating system. For example, avoiding a particular
|
|
sequence of code, or configuring the processor in a particular way. A
|
|
less common situation may require similar actions in order to declassify
|
|
a Category A erratum into a Category C erratum. These are collectively
|
|
known as "software workarounds" and are only required in the minority of
|
|
cases (e.g. those cases that both require a non-secure workaround *and*
|
|
can be triggered by Linux).
|
|
|
|
For software workarounds that may adversely impact systems unaffected by
|
|
the erratum in question, a Kconfig entry is added under "Kernel
|
|
Features" -> "ARM errata workarounds via the alternatives framework".
|
|
These are enabled by default and patched in at runtime when an affected
|
|
CPU is detected. For less-intrusive workarounds, a Kconfig option is not
|
|
available and the code is structured (preferably with a comment) in such
|
|
a way that the erratum will not be hit.
|
|
|
|
This approach can make it slightly onerous to determine exactly which
|
|
errata are worked around in an arbitrary kernel source tree, so this
|
|
file acts as a registry of software workarounds in the Linux Kernel and
|
|
will be updated when new workarounds are committed and backported to
|
|
stable kernels.
|
|
|
|
| Implementor | Component | Erratum ID | Kconfig |
|
|
+----------------+-----------------+-----------------+-------------------------+
|
|
| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
|
|
| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
|
|
| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
|
|
| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
|
|
| ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 |
|
|
| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 |
|
|
| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
|
|
| ARM | Cortex-A57 | #852523 | N/A |
|
|
| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
|
|
| ARM | MMU-500 | #841119,#826419 | N/A |
|
|
| | | | |
|
|
| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
|
|
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
|
|
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
|
|
| Cavium | ThunderX SMMUv2 | #27704 | N/A |
|