mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 08:18:12 +07:00
1009aa1205
This tag contains some major improvements to the RISC-V port, including
the necessary interrupt controller and timer support to actually make it
to userspace. Support for three devices has been added:
* Support for the ISA-mandated timers on RISC-V systems.
* Support for the ISA-mandated first-level interrupt controller on
RISC-V systems, which is handled as part of our core arch code because
it's very small and tightly tied to the ISA.
* Support for SiFive's platform-level interrupt controller, which talks
to the actual devices.
In addition to these new devices, there are a handful of cleanups all
over the RISC-V tree:
* Build fixes for various configurations
* A fix to the vDSO build's makefile so it respects CFLAGS.
* The addition of __lshrti3, a libgcc derived function necessary for
some 32-bit configurations.
* !SMP && PERF_EVENTS
* Cleanups to the arch code to remove the remnants of old versions of
the drivers that were just properly submitted.
* Some dead code from the timer driver, most of which wasn't ever
even compiled.
* Cleanups of some interrupt #defines, which are now local to the
interrupt handling code.
* Fixes to ptrace(), which while not being sufficient to fully make GDB
work are at least sufficient to get simple GDB tasks to work.
* Early printk support via RISC-V's architecturally mandated SBI console
device.
* A fix to our early debug trap handler to ensure it's always aligned.
These patches have all been through a fairly extensive review process,
but as this enables a whole pile of functionality (ie, userspace) I'm
confident we'll need to submit a few more patches. The only concrete
issues I know about are the sys_riscv_flush_icache patches, but as I
managed to screw those up on Friday I figured it'd be best to let them
bake another week.
This tag boots a Fedora root filesystem on QEMU's master branch for me,
and before this morning's rebase (from 4.18-rc8 to 4.18) it booted on
the HiFive Unleashed.
Thanks to Christoph Hellwig and the other guys at WD for getting the new
drivers in shape!
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Merge tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux
Pull RISC-V updates from Palmer Dabbelt:
"This contains some major improvements to the RISC-V port, including
the necessary interrupt controller and timer support to actually make
it to userspace. Support for three devices has been added:
- the ISA-mandated timers on RISC-V systems.
- the ISA-mandated first-level interrupt controller on RISC-V
systems, which is handled as part of our core arch code because
it's very small and tightly tied to the ISA.
- SiFive's platform-level interrupt controller, which talks to the
actual devices.
In addition to these new devices, there are a handful of cleanups all
over the RISC-V tree:
- build fixes for various configurations:
* A fix to the vDSO build's makefile so it respects CFLAGS.
* The addition of __lshrti3, a libgcc derived function necessary
for some 32-bit configurations.
* !SMP && PERF_EVENTS
- Cleanups to the arch code to remove the remnants of old versions of
the drivers that were just properly submitted.
* Some dead code from the timer driver, most of which wasn't ever
even compiled.
* Cleanups of some interrupt #defines, which are now local to the
interrupt handling code.
- Fixes to ptrace(), which while not being sufficient to fully make
GDB work are at least sufficient to get simple GDB tasks to work.
- Early printk support via RISC-V's architecturally mandated SBI
console device.
- A fix to our early debug trap handler to ensure it's always
aligned.
These patches have all been through a fairly extensive review process,
but as this enables a whole pile of functionality (ie, userspace) I'm
confident we'll need to submit a few more patches. The only concrete
issues I know about are the sys_riscv_flush_icache patches, but as I
managed to screw those up on Friday I figured it'd be best to let them
bake another week.
This tag boots a Fedora root filesystem on QEMU's master branch for
me, and before this morning's rebase (from 4.18-rc8 to 4.18) it booted
on the HiFive Unleashed.
Thanks to Christoph Hellwig and the other guys at WD for getting the
new drivers in shape!"
* tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux:
dt-bindings: interrupt-controller: SiFive Plaform Level Interrupt Controller
dt-bindings: interrupt-controller: RISC-V local interrupt controller
RISC-V: Fix !CONFIG_SMP compilation error
irqchip: add a SiFive PLIC driver
RISC-V: Add the directive for alignment of stvec's value
clocksource: new RISC-V SBI timer driver
RISC-V: implement low-level interrupt handling
RISC-V: add a definition for the SIE SEIE bit
RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h
RISC-V: simplify software interrupt / IPI code
RISC-V: remove timer leftovers
RISC-V: Add early printk support via the SBI console
RISC-V: Don't increment sepc after breakpoint.
RISC-V: implement __lshrti3.
RISC-V: Use KBUILD_CFLAGS instead of KCFLAGS when building the vDSO
82 lines
3.6 KiB
Makefile
82 lines
3.6 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_TIMER_OF) += timer-of.o
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obj-$(CONFIG_TIMER_PROBE) += timer-probe.o
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obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o
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obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o
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obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
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obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
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obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
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obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o
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obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o
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obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o
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obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o
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obj-$(CONFIG_RENESAS_OSTM) += renesas-ostm.o
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obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
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obj-$(CONFIG_EM_TIMER_STI) += em_sti.o
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obj-$(CONFIG_CLKBLD_I8253) += i8253.o
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obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
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obj-$(CONFIG_DIGICOLOR_TIMER) += timer-digicolor.o
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obj-$(CONFIG_OMAP_DM_TIMER) += timer-ti-dm.o
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obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o
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obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o
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obj-$(CONFIG_FTTMR010_TIMER) += timer-fttmr010.o
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obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
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obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o
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obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
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obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
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obj-$(CONFIG_ORION_TIMER) += time-orion.o
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obj-$(CONFIG_BCM2835_TIMER) += bcm2835_timer.o
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obj-$(CONFIG_CLPS711X_TIMER) += clps711x-timer.o
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obj-$(CONFIG_ATLAS7_TIMER) += timer-atlas7.o
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obj-$(CONFIG_MXS_TIMER) += mxs_timer.o
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obj-$(CONFIG_CLKSRC_PXA) += pxa_timer.o
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obj-$(CONFIG_PRIMA2_TIMER) += timer-prima2.o
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obj-$(CONFIG_U300_TIMER) += timer-u300.o
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obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o
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obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o
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obj-$(CONFIG_MESON6_TIMER) += meson6_timer.o
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obj-$(CONFIG_TEGRA_TIMER) += tegra20_timer.o
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obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
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obj-$(CONFIG_NSPIRE_TIMER) += zevio-timer.o
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obj-$(CONFIG_BCM_KONA_TIMER) += bcm_kona_timer.o
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obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence_ttc_timer.o
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obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o
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obj-$(CONFIG_CLKSRC_STM32) += timer-stm32.o
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obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
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obj-$(CONFIG_CLKSRC_LPC32XX) += time-lpc32xx.o
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obj-$(CONFIG_CLKSRC_MPS2) += mps2-timer.o
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obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o
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obj-$(CONFIG_FSL_FTM_TIMER) += fsl_ftm_timer.o
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obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o
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obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
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obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o
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obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
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obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
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obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
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obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o
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obj-$(CONFIG_OWL_TIMER) += owl-timer.o
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obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
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obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o
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obj-$(CONFIG_ARC_TIMERS) += arc_timer.o
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obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
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obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
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obj-$(CONFIG_ARMV7M_SYSTICK) += armv7m_systick.o
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obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp804.o
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obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST) += dummy_timer.o
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obj-$(CONFIG_KEYSTONE_TIMER) += timer-keystone.o
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obj-$(CONFIG_INTEGRATOR_AP_TIMER) += timer-integrator-ap.o
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obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o
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obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o
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obj-$(CONFIG_CLKSRC_TANGO_XTAL) += tango_xtal.o
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obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o
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obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o
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obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o
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obj-$(CONFIG_H8300_TMR8) += h8300_timer8.o
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obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o
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obj-$(CONFIG_H8300_TPU) += h8300_tpu.o
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obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
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obj-$(CONFIG_X86_NUMACHIP) += numachip.o
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obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o
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obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
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