mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 08:16:42 +07:00
e6308b6d35
Bridge ASIC is widely used in different SGI systems, but the connected
chipset is either HUB, HEART or BEDROCK. This commit switches to
irq domain hierarchy for hub and bridge interrupts to get bridge
setup out of hub interrupt code.
Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
[paul.burton@mips.com:
Resolve conflict with commit 69a07a41d9
("MIPS: SGI-IP27: rework HUB
interrupts").]
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
611 lines
16 KiB
C
611 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
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* Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/pci.h>
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#include <linux/smp.h>
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#include <linux/dma-direct.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/xtalk-bridge.h>
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#include <asm/pci/bridge.h>
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#include <asm/paccess.h>
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#include <asm/sn/irq_alloc.h>
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/*
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* Most of the IOC3 PCI config register aren't present
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* we emulate what is needed for a normal PCI enumeration
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*/
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static u32 emulate_ioc3_cfg(int where, int size)
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{
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if (size == 1 && where == 0x3d)
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return 0x01;
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else if (size == 2 && where == 0x3c)
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return 0x0100;
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else if (size == 4 && where == 0x3c)
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return 0x00000100;
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return 0;
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}
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static void bridge_disable_swapping(struct pci_dev *dev)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
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int slot = PCI_SLOT(dev->devfn);
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/* Turn off byte swapping */
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bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
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bridge_read(bc, b_widget.w_tflush); /* Flush */
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
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bridge_disable_swapping);
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/*
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* The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
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* not really documented, so right now I can't write code which uses it.
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* Therefore we use type 0 accesses for now even though they won't work
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* correctly for PCI-to-PCI bridges.
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*
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* The function is complicated by the ultimate brokenness of the IOC3 chip
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* which is used in SGI systems. The IOC3 can only handle 32-bit PCI
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* accesses and does only decode parts of it's address space.
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*/
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static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
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struct bridge_regs *bridge = bc->base;
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int slot = PCI_SLOT(devfn);
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int fn = PCI_FUNC(devfn);
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void *addr;
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u32 cf, shift, mask;
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int res;
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
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if (get_dbe(cf, (u32 *)addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* IOC3 is broken beyond belief ... Don't even give the
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* generic PCI code a chance to look at it for real ...
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*/
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
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goto is_ioc3;
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
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if (size == 1)
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res = get_dbe(*value, (u8 *)addr);
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else if (size == 2)
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res = get_dbe(*value, (u16 *)addr);
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else
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res = get_dbe(*value, (u32 *)addr);
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return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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is_ioc3:
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/*
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* IOC3 special handling
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*/
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if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
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*value = emulate_ioc3_cfg(where, size);
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return PCIBIOS_SUCCESSFUL;
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}
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
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if (get_dbe(cf, (u32 *)addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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shift = ((where & 3) << 3);
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mask = (0xffffffffU >> ((4 - size) << 3));
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*value = (cf >> shift) & mask;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
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struct bridge_regs *bridge = bc->base;
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int busno = bus->number;
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int slot = PCI_SLOT(devfn);
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int fn = PCI_FUNC(devfn);
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void *addr;
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u32 cf, shift, mask;
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int res;
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bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
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addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
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if (get_dbe(cf, (u32 *)addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* IOC3 is broken beyond belief ... Don't even give the
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* generic PCI code a chance to look at it for real ...
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*/
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
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goto is_ioc3;
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addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
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if (size == 1)
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res = get_dbe(*value, (u8 *)addr);
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else if (size == 2)
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res = get_dbe(*value, (u16 *)addr);
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else
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res = get_dbe(*value, (u32 *)addr);
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return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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is_ioc3:
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/*
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* IOC3 special handling
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*/
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if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
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*value = emulate_ioc3_cfg(where, size);
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return PCIBIOS_SUCCESSFUL;
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}
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addr = &bridge->b_type1_cfg.c[(fn << 8) | where];
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if (get_dbe(cf, (u32 *)addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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shift = ((where & 3) << 3);
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mask = (0xffffffffU >> ((4 - size) << 3));
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*value = (cf >> shift) & mask;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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if (!pci_is_root_bus(bus))
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return pci_conf1_read_config(bus, devfn, where, size, value);
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return pci_conf0_read_config(bus, devfn, where, size, value);
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}
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static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
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struct bridge_regs *bridge = bc->base;
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int slot = PCI_SLOT(devfn);
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int fn = PCI_FUNC(devfn);
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void *addr;
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u32 cf, shift, mask, smask;
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int res;
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
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if (get_dbe(cf, (u32 *)addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* IOC3 is broken beyond belief ... Don't even give the
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* generic PCI code a chance to look at it for real ...
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*/
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
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goto is_ioc3;
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
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if (size == 1)
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res = put_dbe(value, (u8 *)addr);
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else if (size == 2)
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res = put_dbe(value, (u16 *)addr);
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else
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res = put_dbe(value, (u32 *)addr);
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if (res)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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is_ioc3:
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/*
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* IOC3 special handling
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*/
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if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
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return PCIBIOS_SUCCESSFUL;
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
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if (get_dbe(cf, (u32 *)addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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shift = ((where & 3) << 3);
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mask = (0xffffffffU >> ((4 - size) << 3));
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smask = mask << shift;
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cf = (cf & ~smask) | ((value & mask) << shift);
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if (put_dbe(cf, (u32 *)addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
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struct bridge_regs *bridge = bc->base;
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int slot = PCI_SLOT(devfn);
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int fn = PCI_FUNC(devfn);
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int busno = bus->number;
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void *addr;
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u32 cf, shift, mask, smask;
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int res;
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bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
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addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
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if (get_dbe(cf, (u32 *)addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* IOC3 is broken beyond belief ... Don't even give the
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* generic PCI code a chance to look at it for real ...
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*/
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
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goto is_ioc3;
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addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
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if (size == 1)
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res = put_dbe(value, (u8 *)addr);
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else if (size == 2)
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res = put_dbe(value, (u16 *)addr);
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else
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res = put_dbe(value, (u32 *)addr);
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if (res)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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is_ioc3:
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/*
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* IOC3 special handling
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*/
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if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
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return PCIBIOS_SUCCESSFUL;
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
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if (get_dbe(cf, (u32 *)addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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shift = ((where & 3) << 3);
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mask = (0xffffffffU >> ((4 - size) << 3));
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smask = mask << shift;
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cf = (cf & ~smask) | ((value & mask) << shift);
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if (put_dbe(cf, (u32 *)addr))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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if (!pci_is_root_bus(bus))
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return pci_conf1_write_config(bus, devfn, where, size, value);
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return pci_conf0_write_config(bus, devfn, where, size, value);
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}
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static struct pci_ops bridge_pci_ops = {
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.read = pci_read_config,
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.write = pci_write_config,
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};
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struct bridge_irq_chip_data {
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struct bridge_controller *bc;
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nasid_t nasid;
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};
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static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask,
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bool force)
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{
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#ifdef CONFIG_NUMA
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struct bridge_irq_chip_data *data = d->chip_data;
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int bit = d->parent_data->hwirq;
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int pin = d->hwirq;
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nasid_t nasid;
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int ret, cpu;
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ret = irq_chip_set_affinity_parent(d, mask, force);
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if (ret >= 0) {
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cpu = cpumask_first_and(mask, cpu_online_mask);
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nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
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bridge_write(data->bc, b_int_addr[pin].addr,
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(((data->bc->intr_addr >> 30) & 0x30000) |
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bit | (nasid << 8)));
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bridge_read(data->bc, b_wid_tflush);
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}
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return ret;
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#else
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return irq_chip_set_affinity_parent(d, mask, force);
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#endif
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}
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struct irq_chip bridge_irq_chip = {
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.name = "BRIDGE",
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_set_affinity = bridge_set_affinity
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};
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static int bridge_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct bridge_irq_chip_data *data;
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struct irq_alloc_info *info = arg;
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int ret;
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if (nr_irqs > 1 || !info)
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return -EINVAL;
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
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if (ret >= 0) {
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data->bc = info->ctrl;
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data->nasid = info->nasid;
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irq_domain_set_info(domain, virq, info->pin, &bridge_irq_chip,
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data, handle_level_irq, NULL, NULL);
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} else {
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kfree(data);
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}
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return ret;
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}
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static void bridge_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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struct irq_data *irqd = irq_domain_get_irq_data(domain, virq);
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if (nr_irqs)
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return;
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kfree(irqd->chip_data);
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irq_domain_free_irqs_top(domain, virq, nr_irqs);
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}
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static int bridge_domain_activate(struct irq_domain *domain,
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struct irq_data *irqd, bool reserve)
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{
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struct bridge_irq_chip_data *data = irqd->chip_data;
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struct bridge_controller *bc = data->bc;
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int bit = irqd->parent_data->hwirq;
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int pin = irqd->hwirq;
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u32 device;
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bridge_write(bc, b_int_addr[pin].addr,
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(((bc->intr_addr >> 30) & 0x30000) |
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bit | (data->nasid << 8)));
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bridge_set(bc, b_int_enable, (1 << pin));
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bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */
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/*
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* Enable sending of an interrupt clear packt to the hub on a high to
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* low transition of the interrupt pin.
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*
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* IRIX sets additional bits in the address which are documented as
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* reserved in the bridge docs.
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*/
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bridge_set(bc, b_int_mode, (1UL << pin));
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/*
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* We assume the bridge to have a 1:1 mapping between devices
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* (slots) and intr pins.
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*/
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device = bridge_read(bc, b_int_device);
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device &= ~(7 << (pin*3));
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device |= (pin << (pin*3));
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bridge_write(bc, b_int_device, device);
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bridge_read(bc, b_wid_tflush);
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return 0;
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}
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static void bridge_domain_deactivate(struct irq_domain *domain,
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struct irq_data *irqd)
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{
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struct bridge_irq_chip_data *data = irqd->chip_data;
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bridge_clr(data->bc, b_int_enable, (1 << irqd->hwirq));
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bridge_read(data->bc, b_wid_tflush);
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}
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static const struct irq_domain_ops bridge_domain_ops = {
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.alloc = bridge_domain_alloc,
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.free = bridge_domain_free,
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.activate = bridge_domain_activate,
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.deactivate = bridge_domain_deactivate
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};
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/*
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* All observed requests have pin == 1. We could have a global here, that
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* gets incremented and returned every time - unfortunately, pci_map_irq
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* may be called on the same device over and over, and need to return the
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* same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
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*
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* A given PCI device, in general, should be able to intr any of the cpus
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* on any one of the hubs connected to its xbow.
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*/
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static int bridge_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
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struct irq_alloc_info info;
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int irq;
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irq = bc->pci_int[slot];
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if (irq == -1) {
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info.ctrl = bc;
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info.nasid = bc->nasid;
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info.pin = slot;
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irq = irq_domain_alloc_irqs(bc->domain, 1, bc->nasid, &info);
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if (irq < 0)
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return irq;
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bc->pci_int[slot] = irq;
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}
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return irq;
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}
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static int bridge_probe(struct platform_device *pdev)
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{
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struct xtalk_bridge_platform_data *bd = dev_get_platdata(&pdev->dev);
|
|
struct device *dev = &pdev->dev;
|
|
struct bridge_controller *bc;
|
|
struct pci_host_bridge *host;
|
|
struct irq_domain *domain, *parent;
|
|
struct fwnode_handle *fn;
|
|
int slot;
|
|
int err;
|
|
|
|
parent = irq_get_default_host();
|
|
if (!parent)
|
|
return -ENODEV;
|
|
fn = irq_domain_alloc_named_fwnode("BRIDGE");
|
|
if (!fn)
|
|
return -ENOMEM;
|
|
domain = irq_domain_create_hierarchy(parent, 0, 8, fn,
|
|
&bridge_domain_ops, NULL);
|
|
irq_domain_free_fwnode(fn);
|
|
if (!domain)
|
|
return -ENOMEM;
|
|
|
|
pci_set_flags(PCI_PROBE_ONLY);
|
|
|
|
host = devm_pci_alloc_host_bridge(dev, sizeof(*bc));
|
|
if (!host) {
|
|
err = -ENOMEM;
|
|
goto err_remove_domain;
|
|
}
|
|
|
|
bc = pci_host_bridge_priv(host);
|
|
|
|
bc->busn.name = "Bridge PCI busn";
|
|
bc->busn.start = 0;
|
|
bc->busn.end = 0xff;
|
|
bc->busn.flags = IORESOURCE_BUS;
|
|
|
|
bc->domain = domain;
|
|
|
|
pci_add_resource_offset(&host->windows, &bd->mem, bd->mem_offset);
|
|
pci_add_resource_offset(&host->windows, &bd->io, bd->io_offset);
|
|
pci_add_resource(&host->windows, &bc->busn);
|
|
|
|
err = devm_request_pci_bus_resources(dev, &host->windows);
|
|
if (err < 0)
|
|
goto err_free_resource;
|
|
|
|
bc->nasid = bd->nasid;
|
|
|
|
bc->baddr = (u64)bd->masterwid << 60 | PCI64_ATTR_BAR;
|
|
bc->base = (struct bridge_regs *)bd->bridge_addr;
|
|
bc->intr_addr = bd->intr_addr;
|
|
|
|
/*
|
|
* Clear all pending interrupts.
|
|
*/
|
|
bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
|
|
|
|
/*
|
|
* Until otherwise set up, assume all interrupts are from slot 0
|
|
*/
|
|
bridge_write(bc, b_int_device, 0x0);
|
|
|
|
/*
|
|
* disable swapping for big windows
|
|
*/
|
|
bridge_clr(bc, b_wid_control,
|
|
BRIDGE_CTRL_IO_SWAP | BRIDGE_CTRL_MEM_SWAP);
|
|
#ifdef CONFIG_PAGE_SIZE_4KB
|
|
bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
|
|
#else /* 16kB or larger */
|
|
bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
|
|
#endif
|
|
|
|
/*
|
|
* Hmm... IRIX sets additional bits in the address which
|
|
* are documented as reserved in the bridge docs.
|
|
*/
|
|
bridge_write(bc, b_wid_int_upper,
|
|
((bc->intr_addr >> 32) & 0xffff) | (bd->masterwid << 16));
|
|
bridge_write(bc, b_wid_int_lower, bc->intr_addr & 0xffffffff);
|
|
bridge_write(bc, b_dir_map, (bd->masterwid << 20)); /* DMA */
|
|
bridge_write(bc, b_int_enable, 0);
|
|
|
|
for (slot = 0; slot < 8; slot++) {
|
|
bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
|
|
bc->pci_int[slot] = -1;
|
|
}
|
|
bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */
|
|
|
|
host->dev.parent = dev;
|
|
host->sysdata = bc;
|
|
host->busnr = 0;
|
|
host->ops = &bridge_pci_ops;
|
|
host->map_irq = bridge_map_irq;
|
|
host->swizzle_irq = pci_common_swizzle;
|
|
|
|
err = pci_scan_root_bus_bridge(host);
|
|
if (err < 0)
|
|
goto err_free_resource;
|
|
|
|
pci_bus_claim_resources(host->bus);
|
|
pci_bus_add_devices(host->bus);
|
|
|
|
platform_set_drvdata(pdev, host->bus);
|
|
|
|
return 0;
|
|
|
|
err_free_resource:
|
|
pci_free_resource_list(&host->windows);
|
|
err_remove_domain:
|
|
irq_domain_remove(domain);
|
|
return err;
|
|
}
|
|
|
|
static int bridge_remove(struct platform_device *pdev)
|
|
{
|
|
struct pci_bus *bus = platform_get_drvdata(pdev);
|
|
struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
|
|
|
|
irq_domain_remove(bc->domain);
|
|
pci_lock_rescan_remove();
|
|
pci_stop_root_bus(bus);
|
|
pci_remove_root_bus(bus);
|
|
pci_unlock_rescan_remove();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver bridge_driver = {
|
|
.probe = bridge_probe,
|
|
.remove = bridge_remove,
|
|
.driver = {
|
|
.name = "xtalk-bridge",
|
|
}
|
|
};
|
|
|
|
builtin_platform_driver(bridge_driver);
|