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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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40fb17152c
Impact: reward non-stop TSCs with good TSC-based clocksources, etc. Add support for CPUID_0x80000007_Bit8 on Intel CPUs as well. This bit means that the TSC is invariant with C/P/T states and always runs at constant frequency. With Intel CPUs, we have 3 classes * CPUs where TSC runs at constant rate and does not stop n C-states * CPUs where TSC runs at constant rate, but will stop in deep C-states * CPUs where TSC rate will vary based on P/T-states and TSC will stop in deep C-states. To cover these 3, one feature bit (CONSTANT_TSC) is not enough. So, add a second bit (NONSTOP_TSC). CONSTANT_TSC indicates that the TSC runs at constant frequency irrespective of P/T-states, and NONSTOP_TSC indicates that TSC does not stop in deep C-states. CPUID_0x8000000_Bit8 indicates both these feature bit can be set. We still have CONSTANT_TSC _set_ and NONSTOP_TSC _not_set_ on some older Intel CPUs, based on model checks. We can use TSC on such CPUs for time, as long as those CPUs do not support/enter deep C-states. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> |
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| .. | ||
| cpufreq | ||
| mcheck | ||
| mtrr | ||
| .gitignore | ||
| addon_cpuid_features.c | ||
| amd.c | ||
| bugs_64.c | ||
| bugs.c | ||
| centaur_64.c | ||
| centaur.c | ||
| cmpxchg.c | ||
| common.c | ||
| cpu.h | ||
| cyrix.c | ||
| intel_cacheinfo.c | ||
| intel.c | ||
| Makefile | ||
| mkcapflags.pl | ||
| perfctr-watchdog.c | ||
| powerflags.c | ||
| proc.c | ||
| transmeta.c | ||
| umc.c | ||