mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 07:05:08 +07:00
d9c927833a
Commit fad107086d fixed the wrong test for MX51
as the MX51 addresses are wrong for MX50 and MX53 but now it's MX51 only,
UART_PADDR is not defined anymore when building for MX50/MX53.
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Tested-by: Steev Klimaszewski <steev@genesi-usa.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
74 lines
1.8 KiB
ArmAsm
74 lines
1.8 KiB
ArmAsm
/* arch/arm/mach-imx/include/mach/debug-macro.S
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*
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* Debugging macro include header
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*
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* Copyright (C) 1994-1999 Russell King
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* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <mach/hardware.h>
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#ifdef CONFIG_SOC_IMX1
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#define UART_PADDR MX1_UART1_BASE_ADDR
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#endif
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#ifdef CONFIG_SOC_IMX25
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#ifdef UART_PADDR
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#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
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#endif
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#define UART_PADDR MX25_UART1_BASE_ADDR
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#endif
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#if defined(CONFIG_SOC_IMX21) || defined (CONFIG_SOC_IMX27)
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#ifdef UART_PADDR
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#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
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#endif
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#define UART_PADDR MX2x_UART1_BASE_ADDR
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#endif
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#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35)
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#ifdef UART_PADDR
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#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
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#endif
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#define UART_PADDR MX3x_UART1_BASE_ADDR
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#endif
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#ifdef CONFIG_SOC_IMX51
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#ifdef UART_PADDR
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#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
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#endif
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#define UART_PADDR MX51_UART1_BASE_ADDR
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#endif
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/* iMX50/53 have same addresses, but not iMX51 */
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#if defined(CONFIG_SOC_IMX50) || defined(CONFIG_SOC_IMX53)
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#ifdef UART_PADDR
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#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
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#endif
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#define UART_PADDR MX53_UART1_BASE_ADDR
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#endif
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#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR)
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.macro addruart, rp, rv
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ldr \rp, =UART_PADDR @ physical
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ldr \rv, =UART_VADDR @ virtual
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.endm
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.macro senduart,rd,rx
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str \rd, [\rx, #0x40] @ TXDATA
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.endm
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.macro waituart,rd,rx
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.endm
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.macro busyuart,rd,rx
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1002: ldr \rd, [\rx, #0x98] @ SR2
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tst \rd, #1 << 3 @ TXDC
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beq 1002b @ wait until transmit done
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.endm
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