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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a8d9d7da15
AM65x PG1 has a HW issue with YUV pixel formats, resulting in wrong colors on the screen. This issue is fixed in PG2 hardware. The driver currently has code to hide YUV pixel formats from the userspace. To support PG2, we would need to add code to detect the SoC version and hide the YUV formats based on that. However, as PG1 will be phased out and PG2 will be the main platform, a much simpler solution is just to drop the code in question. The downside is that the users will be able to use YUV formats on PG1, getting wrong colors on the screen. On the other hand, that may also be a plus, as the same applications will now work on PG1 and PG2, even if the colors are wrong on PG1. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200429121022.3871-1-tomi.valkeinen@ti.com Reviewed-by: Jyri Sarha <jsarha@ti.com>
132 lines
4.1 KiB
C
132 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
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*/
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#ifndef __TIDSS_DISPC_H__
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#define __TIDSS_DISPC_H__
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#include "tidss_drv.h"
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struct dispc_device;
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struct drm_crtc_state;
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enum tidss_gamma_type { TIDSS_GAMMA_8BIT, TIDSS_GAMMA_10BIT };
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struct tidss_vp_feat {
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struct tidss_vp_color_feat {
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u32 gamma_size;
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enum tidss_gamma_type gamma_type;
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bool has_ctm;
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} color;
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};
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struct tidss_plane_feat {
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struct tidss_plane_color_feat {
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u32 encodings;
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u32 ranges;
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enum drm_color_encoding default_encoding;
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enum drm_color_range default_range;
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} color;
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struct tidss_plane_blend_feat {
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bool global_alpha;
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} blend;
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};
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struct dispc_features_scaling {
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u32 in_width_max_5tap_rgb;
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u32 in_width_max_3tap_rgb;
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u32 in_width_max_5tap_yuv;
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u32 in_width_max_3tap_yuv;
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u32 upscale_limit;
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u32 downscale_limit_5tap;
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u32 downscale_limit_3tap;
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u32 xinc_max;
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};
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enum dispc_vp_bus_type {
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DISPC_VP_DPI, /* DPI output */
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DISPC_VP_OLDI, /* OLDI (LVDS) output */
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DISPC_VP_INTERNAL, /* SoC internal routing */
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DISPC_VP_MAX_BUS_TYPE,
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};
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enum dispc_dss_subrevision {
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DISPC_K2G,
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DISPC_AM65X,
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DISPC_J721E,
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};
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struct dispc_features {
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int min_pclk_khz;
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int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE];
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struct dispc_features_scaling scaling;
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enum dispc_dss_subrevision subrev;
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const char *common;
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const u16 *common_regs;
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u32 num_vps;
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const char *vp_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */
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const char *ovr_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */
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const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */
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const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS];
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struct tidss_vp_feat vp_feat;
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u32 num_planes;
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const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */
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bool vid_lite[TIDSS_MAX_PLANES];
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u32 vid_order[TIDSS_MAX_PLANES];
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};
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extern const struct dispc_features dispc_k2g_feats;
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extern const struct dispc_features dispc_am65x_feats;
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extern const struct dispc_features dispc_j721e_feats;
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void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask);
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dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc);
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void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
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u32 hw_videoport, u32 x, u32 y, u32 layer);
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void dispc_ovr_enable_layer(struct dispc_device *dispc,
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u32 hw_videoport, u32 layer, bool enable);
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void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
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const struct drm_crtc_state *state);
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void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
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const struct drm_crtc_state *state);
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void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport);
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void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport);
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bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport);
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void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport);
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int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport,
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const struct drm_crtc_state *state);
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enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
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u32 hw_videoport,
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const struct drm_display_mode *mode);
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int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport);
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void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport);
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int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
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unsigned long rate);
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void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport,
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const struct drm_crtc_state *state, bool newmodeset);
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int dispc_runtime_suspend(struct dispc_device *dispc);
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int dispc_runtime_resume(struct dispc_device *dispc);
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int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
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const struct drm_plane_state *state,
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u32 hw_videoport);
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int dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
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const struct drm_plane_state *state,
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u32 hw_videoport);
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int dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable);
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const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len);
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int dispc_init(struct tidss_device *tidss);
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void dispc_remove(struct tidss_device *tidss);
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#endif
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