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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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932b50c7c1
The ARM architecture defines the memory locations that are permitted
to be accessed as the result of a speculative instruction fetch from
an exception level for which all stages of translation are disabled.
Specifically, the core is permitted to speculatively fetch from the
4KB region containing the current program counter 4K and next 4K.
When translation is changed from enabled to disabled for the running
exception level (SCTLR_ELn[M] changed from a value of 1 to 0), the
Falkor core may errantly speculatively access memory locations outside
of the 4KB region permitted by the architecture. The errant memory
access may lead to one of the following unexpected behaviors.
1) A System Error Interrupt (SEI) being raised by the Falkor core due
to the errant memory access attempting to access a region of memory
that is protected by a slave-side memory protection unit.
2) Unpredictable device behavior due to a speculative read from device
memory. This behavior may only occur if the instruction cache is
disabled prior to or coincident with translation being changed from
enabled to disabled.
The conditions leading to this erratum will not occur when either of the
following occur:
1) A higher exception level disables translation of a lower exception level
(e.g. EL2 changing SCTLR_EL1[M] from a value of 1 to 0).
2) An exception level disabling its stage-1 translation if its stage-2
translation is enabled (e.g. EL1 changing SCTLR_EL1[M] from a value of 1
to 0 when HCR_EL2[VM] has a value of 1).
To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
173 lines
4.1 KiB
ArmAsm
173 lines
4.1 KiB
ArmAsm
/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_mmu.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/sysreg.h>
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#include <asm/virt.h>
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.text
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.pushsection .hyp.idmap.text, "ax"
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.align 11
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ENTRY(__kvm_hyp_init)
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ventry __invalid // Synchronous EL2t
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ventry __invalid // IRQ EL2t
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ventry __invalid // FIQ EL2t
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ventry __invalid // Error EL2t
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ventry __invalid // Synchronous EL2h
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ventry __invalid // IRQ EL2h
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ventry __invalid // FIQ EL2h
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ventry __invalid // Error EL2h
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ventry __do_hyp_init // Synchronous 64-bit EL1
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ventry __invalid // IRQ 64-bit EL1
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ventry __invalid // FIQ 64-bit EL1
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ventry __invalid // Error 64-bit EL1
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ventry __invalid // Synchronous 32-bit EL1
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ventry __invalid // IRQ 32-bit EL1
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ventry __invalid // FIQ 32-bit EL1
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ventry __invalid // Error 32-bit EL1
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__invalid:
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b .
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/*
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* x0: HYP pgd
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* x1: HYP stack
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* x2: HYP vectors
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*/
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__do_hyp_init:
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/* Check for a stub HVC call */
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cmp x0, #HVC_STUB_HCALL_NR
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b.lo __kvm_handle_stub_hvc
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msr ttbr0_el2, x0
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mrs x4, tcr_el1
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ldr x5, =TCR_EL2_MASK
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and x4, x4, x5
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mov x5, #TCR_EL2_RES1
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orr x4, x4, x5
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#ifndef CONFIG_ARM64_VA_BITS_48
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/*
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* If we are running with VA_BITS < 48, we may be running with an extra
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* level of translation in the ID map. This is only the case if system
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* RAM is out of range for the currently configured page size and number
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* of translation levels, in which case we will also need the extra
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* level for the HYP ID map, or we won't be able to enable the EL2 MMU.
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*
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* However, at EL2, there is only one TTBR register, and we can't switch
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* between translation tables *and* update TCR_EL2.T0SZ at the same
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* time. Bottom line: we need the extra level in *both* our translation
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* tables.
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*
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* So use the same T0SZ value we use for the ID map.
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*/
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ldr_l x5, idmap_t0sz
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bfi x4, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
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#endif
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/*
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* Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS bits in
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* TCR_EL2.
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*/
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mrs x5, ID_AA64MMFR0_EL1
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bfi x4, x5, #16, #3
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msr tcr_el2, x4
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mrs x4, mair_el1
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msr mair_el2, x4
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isb
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/* Invalidate the stale TLBs from Bootloader */
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tlbi alle2
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dsb sy
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/*
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* Preserve all the RES1 bits while setting the default flags,
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* as well as the EE bit on BE. Drop the A flag since the compiler
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* is allowed to generate unaligned accesses.
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*/
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ldr x4, =(SCTLR_EL2_RES1 | (SCTLR_ELx_FLAGS & ~SCTLR_ELx_A))
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CPU_BE( orr x4, x4, #SCTLR_ELx_EE)
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msr sctlr_el2, x4
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isb
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/* Set the stack and new vectors */
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kern_hyp_va x1
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mov sp, x1
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kern_hyp_va x2
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msr vbar_el2, x2
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/* Hello, World! */
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eret
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ENDPROC(__kvm_hyp_init)
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ENTRY(__kvm_handle_stub_hvc)
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cmp x0, #HVC_SOFT_RESTART
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b.ne 1f
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/* This is where we're about to jump, staying at EL2 */
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msr elr_el2, x1
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mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT | PSR_MODE_EL2h)
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msr spsr_el2, x0
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/* Shuffle the arguments, and don't come back */
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mov x0, x2
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mov x1, x3
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mov x2, x4
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b reset
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1: cmp x0, #HVC_RESET_VECTORS
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b.ne 1f
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reset:
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/*
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* Reset kvm back to the hyp stub. Do not clobber x0-x4 in
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* case we coming via HVC_SOFT_RESTART.
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*/
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mrs x5, sctlr_el2
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ldr x6, =SCTLR_ELx_FLAGS
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bic x5, x5, x6 // Clear SCTL_M and etc
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pre_disable_mmu_workaround
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msr sctlr_el2, x5
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isb
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/* Install stub vectors */
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adr_l x5, __hyp_stub_vectors
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msr vbar_el2, x5
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mov x0, xzr
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eret
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1: /* Bad stub call */
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ldr x0, =HVC_STUB_ERR
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eret
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ENDPROC(__kvm_handle_stub_hvc)
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.ltorg
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.popsection
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