mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 04:45:12 +07:00
4060bbe993
Now that the MIPS GIC irqchip lives in drivers/irqchip/, move its header over to include/linux/irqchip/. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8129/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
326 lines
11 KiB
C
326 lines
11 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000, 07 MIPS Technologies, Inc.
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*
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* GIC Register Definitions
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*
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*/
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#ifndef _ASM_GICREGS_H
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#define _ASM_GICREGS_H
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#include <linux/bitmap.h>
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#include <linux/threads.h>
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#include <irq.h>
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#define GIC_MAX_INTRS 256
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/* Constants */
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#define GIC_POL_POS 1
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#define GIC_POL_NEG 0
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#define GIC_TRIG_EDGE 1
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#define GIC_TRIG_LEVEL 0
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#define GIC_TRIG_DUAL_ENABLE 1
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#define GIC_TRIG_DUAL_DISABLE 0
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#define MSK(n) ((1 << (n)) - 1)
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/* Accessors */
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#define GIC_REG(segment, offset) (segment##_##SECTION_OFS + offset##_##OFS)
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/* GIC Address Space */
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#define SHARED_SECTION_OFS 0x0000
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#define SHARED_SECTION_SIZE 0x8000
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#define VPE_LOCAL_SECTION_OFS 0x8000
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#define VPE_LOCAL_SECTION_SIZE 0x4000
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#define VPE_OTHER_SECTION_OFS 0xc000
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#define VPE_OTHER_SECTION_SIZE 0x4000
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#define USM_VISIBLE_SECTION_OFS 0x10000
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#define USM_VISIBLE_SECTION_SIZE 0x10000
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/* Register Map for Shared Section */
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#define GIC_SH_CONFIG_OFS 0x0000
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/* Shared Global Counter */
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#define GIC_SH_COUNTER_31_00_OFS 0x0010
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#define GIC_SH_COUNTER_63_32_OFS 0x0014
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#define GIC_SH_REVISIONID_OFS 0x0020
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/* Interrupt Polarity */
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#define GIC_SH_POL_31_0_OFS 0x0100
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#define GIC_SH_POL_63_32_OFS 0x0104
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#define GIC_SH_POL_95_64_OFS 0x0108
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#define GIC_SH_POL_127_96_OFS 0x010c
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#define GIC_SH_POL_159_128_OFS 0x0110
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#define GIC_SH_POL_191_160_OFS 0x0114
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#define GIC_SH_POL_223_192_OFS 0x0118
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#define GIC_SH_POL_255_224_OFS 0x011c
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/* Edge/Level Triggering */
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#define GIC_SH_TRIG_31_0_OFS 0x0180
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#define GIC_SH_TRIG_63_32_OFS 0x0184
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#define GIC_SH_TRIG_95_64_OFS 0x0188
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#define GIC_SH_TRIG_127_96_OFS 0x018c
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#define GIC_SH_TRIG_159_128_OFS 0x0190
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#define GIC_SH_TRIG_191_160_OFS 0x0194
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#define GIC_SH_TRIG_223_192_OFS 0x0198
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#define GIC_SH_TRIG_255_224_OFS 0x019c
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/* Dual Edge Triggering */
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#define GIC_SH_DUAL_31_0_OFS 0x0200
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#define GIC_SH_DUAL_63_32_OFS 0x0204
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#define GIC_SH_DUAL_95_64_OFS 0x0208
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#define GIC_SH_DUAL_127_96_OFS 0x020c
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#define GIC_SH_DUAL_159_128_OFS 0x0210
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#define GIC_SH_DUAL_191_160_OFS 0x0214
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#define GIC_SH_DUAL_223_192_OFS 0x0218
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#define GIC_SH_DUAL_255_224_OFS 0x021c
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/* Set/Clear corresponding bit in Edge Detect Register */
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#define GIC_SH_WEDGE_OFS 0x0280
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/* Reset Mask - Disables Interrupt */
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#define GIC_SH_RMASK_31_0_OFS 0x0300
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#define GIC_SH_RMASK_63_32_OFS 0x0304
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#define GIC_SH_RMASK_95_64_OFS 0x0308
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#define GIC_SH_RMASK_127_96_OFS 0x030c
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#define GIC_SH_RMASK_159_128_OFS 0x0310
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#define GIC_SH_RMASK_191_160_OFS 0x0314
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#define GIC_SH_RMASK_223_192_OFS 0x0318
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#define GIC_SH_RMASK_255_224_OFS 0x031c
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/* Set Mask (WO) - Enables Interrupt */
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#define GIC_SH_SMASK_31_0_OFS 0x0380
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#define GIC_SH_SMASK_63_32_OFS 0x0384
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#define GIC_SH_SMASK_95_64_OFS 0x0388
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#define GIC_SH_SMASK_127_96_OFS 0x038c
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#define GIC_SH_SMASK_159_128_OFS 0x0390
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#define GIC_SH_SMASK_191_160_OFS 0x0394
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#define GIC_SH_SMASK_223_192_OFS 0x0398
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#define GIC_SH_SMASK_255_224_OFS 0x039c
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/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
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#define GIC_SH_MASK_31_0_OFS 0x0400
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#define GIC_SH_MASK_63_32_OFS 0x0404
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#define GIC_SH_MASK_95_64_OFS 0x0408
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#define GIC_SH_MASK_127_96_OFS 0x040c
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#define GIC_SH_MASK_159_128_OFS 0x0410
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#define GIC_SH_MASK_191_160_OFS 0x0414
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#define GIC_SH_MASK_223_192_OFS 0x0418
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#define GIC_SH_MASK_255_224_OFS 0x041c
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/* Pending Global Interrupts (RO) */
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#define GIC_SH_PEND_31_0_OFS 0x0480
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#define GIC_SH_PEND_63_32_OFS 0x0484
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#define GIC_SH_PEND_95_64_OFS 0x0488
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#define GIC_SH_PEND_127_96_OFS 0x048c
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#define GIC_SH_PEND_159_128_OFS 0x0490
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#define GIC_SH_PEND_191_160_OFS 0x0494
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#define GIC_SH_PEND_223_192_OFS 0x0498
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#define GIC_SH_PEND_255_224_OFS 0x049c
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#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
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/* Maps Interrupt X to a Pin */
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#define GIC_SH_MAP_TO_PIN(intr) (4 * (intr))
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#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
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/* Maps Interrupt X to a VPE */
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#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
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((32 * (intr)) + (((vpe) / 32) * 4))
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#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
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/* Convert an interrupt number to a byte offset/bit for multi-word registers */
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#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
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#define GIC_INTR_BIT(intr) ((intr) % 32)
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/* Polarity : Reset Value is always 0 */
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#define GIC_SH_SET_POLARITY_OFS 0x0100
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/* Triggering : Reset Value is always 0 */
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#define GIC_SH_SET_TRIGGER_OFS 0x0180
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/* Dual edge triggering : Reset Value is always 0 */
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#define GIC_SH_SET_DUAL_OFS 0x0200
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/* Mask manipulation */
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#define GIC_SH_SMASK_OFS 0x0380
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#define GIC_SH_RMASK_OFS 0x0300
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/* Register Map for Local Section */
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#define GIC_VPE_CTL_OFS 0x0000
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#define GIC_VPE_PEND_OFS 0x0004
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#define GIC_VPE_MASK_OFS 0x0008
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#define GIC_VPE_RMASK_OFS 0x000c
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#define GIC_VPE_SMASK_OFS 0x0010
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#define GIC_VPE_WD_MAP_OFS 0x0040
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#define GIC_VPE_COMPARE_MAP_OFS 0x0044
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#define GIC_VPE_TIMER_MAP_OFS 0x0048
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#define GIC_VPE_FDC_MAP_OFS 0x004c
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#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
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#define GIC_VPE_SWINT0_MAP_OFS 0x0054
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#define GIC_VPE_SWINT1_MAP_OFS 0x0058
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#define GIC_VPE_OTHER_ADDR_OFS 0x0080
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#define GIC_VPE_WD_CONFIG0_OFS 0x0090
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#define GIC_VPE_WD_COUNT0_OFS 0x0094
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#define GIC_VPE_WD_INITIAL0_OFS 0x0098
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#define GIC_VPE_COMPARE_LO_OFS 0x00a0
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#define GIC_VPE_COMPARE_HI_OFS 0x00a4
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#define GIC_VPE_EIC_SHADOW_SET_BASE_OFS 0x0100
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#define GIC_VPE_EIC_SS(intr) (4 * (intr))
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#define GIC_VPE_EIC_VEC_BASE_OFS 0x0800
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#define GIC_VPE_EIC_VEC(intr) (4 * (intr))
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#define GIC_VPE_TENABLE_NMI_OFS 0x1000
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#define GIC_VPE_TENABLE_YQ_OFS 0x1004
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#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
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#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
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/* User Mode Visible Section Register Map */
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#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
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#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
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/* Masks */
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#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
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#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
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#define GIC_SH_CONFIG_COUNTBITS_SHF 24
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#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
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#define GIC_SH_CONFIG_NUMINTRS_SHF 16
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#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
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#define GIC_SH_CONFIG_NUMVPES_SHF 0
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#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
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#define GIC_SH_WEDGE_SET(intr) (intr | (0x1 << 31))
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#define GIC_SH_WEDGE_CLR(intr) (intr & ~(0x1 << 31))
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#define GIC_MAP_TO_PIN_SHF 31
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#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
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#define GIC_MAP_TO_NMI_SHF 30
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#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
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#define GIC_MAP_TO_YQ_SHF 29
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#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
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#define GIC_MAP_SHF 0
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#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
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/* GIC_VPE_CTL Masks */
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#define GIC_VPE_CTL_FDC_RTBL_SHF 4
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#define GIC_VPE_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VPE_CTL_FDC_RTBL_SHF)
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#define GIC_VPE_CTL_SWINT_RTBL_SHF 3
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#define GIC_VPE_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_SWINT_RTBL_SHF)
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#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
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#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
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#define GIC_VPE_CTL_TIMER_RTBL_SHF 1
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#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
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#define GIC_VPE_CTL_EIC_MODE_SHF 0
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#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
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/* GIC_VPE_PEND Masks */
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#define GIC_VPE_PEND_WD_SHF 0
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#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF)
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#define GIC_VPE_PEND_CMP_SHF 1
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#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF)
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#define GIC_VPE_PEND_TIMER_SHF 2
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#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
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#define GIC_VPE_PEND_PERFCOUNT_SHF 3
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#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
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#define GIC_VPE_PEND_SWINT0_SHF 4
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#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
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#define GIC_VPE_PEND_SWINT1_SHF 5
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#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
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/* GIC_VPE_RMASK Masks */
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#define GIC_VPE_RMASK_WD_SHF 0
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#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF)
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#define GIC_VPE_RMASK_CMP_SHF 1
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#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
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#define GIC_VPE_RMASK_TIMER_SHF 2
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#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
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#define GIC_VPE_RMASK_PERFCNT_SHF 3
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#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
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#define GIC_VPE_RMASK_SWINT0_SHF 4
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#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
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#define GIC_VPE_RMASK_SWINT1_SHF 5
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#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
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/* GIC_VPE_SMASK Masks */
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#define GIC_VPE_SMASK_WD_SHF 0
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#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF)
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#define GIC_VPE_SMASK_CMP_SHF 1
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#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
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#define GIC_VPE_SMASK_TIMER_SHF 2
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#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
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#define GIC_VPE_SMASK_PERFCNT_SHF 3
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#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
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#define GIC_VPE_SMASK_SWINT0_SHF 4
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#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
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#define GIC_VPE_SMASK_SWINT1_SHF 5
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#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
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/* GIC nomenclature for Core Interrupt Pins. */
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#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
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#define GIC_CPU_INT1 1 /* . */
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#define GIC_CPU_INT2 2 /* . */
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#define GIC_CPU_INT3 3 /* . */
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#define GIC_CPU_INT4 4 /* . */
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#define GIC_CPU_INT5 5 /* Core Interrupt 7 */
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/* Add 2 to convert GIC CPU pin to core interrupt */
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#define GIC_CPU_PIN_OFFSET 2
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/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
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#define GIC_CPU_TO_VEC_OFFSET (2)
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/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
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#define GIC_PIN_TO_VEC_OFFSET (1)
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/* Local GIC interrupts. */
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#define GIC_LOCAL_INT_WD 0 /* GIC watchdog */
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#define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */
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#define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */
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#define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */
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#define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */
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#define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */
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#define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */
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#define GIC_NUM_LOCAL_INTRS 7
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/* Convert between local/shared IRQ number and GIC HW IRQ number. */
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#define GIC_LOCAL_HWIRQ_BASE 0
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#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x))
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#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
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#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
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#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
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#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
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#include <linux/clocksource.h>
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#include <linux/irq.h>
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extern unsigned int gic_present;
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extern unsigned int gic_frequency;
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extern void gic_init(unsigned long gic_base_addr,
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unsigned long gic_addrspace_size, unsigned int cpu_vec,
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unsigned int irqbase);
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extern void gic_clocksource_init(unsigned int);
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extern cycle_t gic_read_count(void);
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extern unsigned int gic_get_count_width(void);
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extern cycle_t gic_read_compare(void);
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extern void gic_write_compare(cycle_t cnt);
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extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
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extern void gic_send_ipi(unsigned int intr);
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extern unsigned int plat_ipi_call_int_xlate(unsigned int);
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extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
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extern unsigned int gic_get_timer_pending(void);
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extern int gic_get_c0_compare_int(void);
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extern int gic_get_c0_perfcount_int(void);
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#endif /* _ASM_GICREGS_H */
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