mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
3fdbf004c1
Instead of adapting the CPU family check in amd_special_default_mtrr() for each new CPU family assume that all new AMD CPUs support the necessary bits in SYS_CFG MSR. Tom2Enabled is architectural (defined in APM Vol.2). Tom2ForceMemTypeWB is defined in all BKDGs starting with K8 NPT. In pre K8-NPT BKDG this bit is reserved (read as zero). W/o this adaption Linux would unnecessarily complain about bad MTRR settings on every new AMD CPU family, e.g. [ 0.000000] WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 4863MB of RAM. Cc: stable@kernel.org # .32.x, .35.x Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> LKML-Reference: <20100930123235.GB20545@loge.amd.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> |
||
---|---|---|
.. | ||
cpufreq | ||
mcheck | ||
mtrr | ||
.gitignore | ||
amd.c | ||
bugs_64.c | ||
bugs.c | ||
centaur.c | ||
common.c | ||
cpu.h | ||
cyrix.c | ||
hypervisor.c | ||
intel_cacheinfo.c | ||
intel.c | ||
Makefile | ||
mkcapflags.pl | ||
mshyperv.c | ||
perf_event_amd.c | ||
perf_event_intel_ds.c | ||
perf_event_intel_lbr.c | ||
perf_event_intel.c | ||
perf_event_p4.c | ||
perf_event_p6.c | ||
perf_event.c | ||
perfctr-watchdog.c | ||
powerflags.c | ||
proc.c | ||
scattered.c | ||
sched.c | ||
topology.c | ||
transmeta.c | ||
umc.c | ||
vmware.c |