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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c4dcc8a162
It always returns 0 (success) and its return type should really be void. Over that, many drivers have added error handling code based on its return value, which is not required at all. Change its return type to void and update all the callers. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
222 lines
5.8 KiB
C
222 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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* Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
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*/
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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static struct cpufreq_frequency_table freq_table[] = {
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{ .frequency = 216000 },
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{ .frequency = 312000 },
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{ .frequency = 456000 },
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{ .frequency = 608000 },
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{ .frequency = 760000 },
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{ .frequency = 816000 },
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{ .frequency = 912000 },
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{ .frequency = 1000000 },
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{ .frequency = CPUFREQ_TABLE_END },
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};
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struct tegra20_cpufreq {
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struct device *dev;
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struct cpufreq_driver driver;
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struct clk *cpu_clk;
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struct clk *pll_x_clk;
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struct clk *pll_p_clk;
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bool pll_x_prepared;
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};
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static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy,
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unsigned int index)
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{
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struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data();
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unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000;
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/*
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* Don't switch to intermediate freq if:
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* - we are already at it, i.e. policy->cur == ifreq
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* - index corresponds to ifreq
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*/
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if (freq_table[index].frequency == ifreq || policy->cur == ifreq)
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return 0;
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return ifreq;
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}
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static int tegra_target_intermediate(struct cpufreq_policy *policy,
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unsigned int index)
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{
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struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data();
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int ret;
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/*
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* Take an extra reference to the main pll so it doesn't turn
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* off when we move the cpu off of it as enabling it again while we
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* switch to it from tegra_target() would take additional time.
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*
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* When target-freq is equal to intermediate freq we don't need to
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* switch to an intermediate freq and so this routine isn't called.
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* Also, we wouldn't be using pll_x anymore and must not take extra
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* reference to it, as it can be disabled now to save some power.
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*/
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clk_prepare_enable(cpufreq->pll_x_clk);
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ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk);
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if (ret)
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clk_disable_unprepare(cpufreq->pll_x_clk);
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else
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cpufreq->pll_x_prepared = true;
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return ret;
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}
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static int tegra_target(struct cpufreq_policy *policy, unsigned int index)
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{
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struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data();
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unsigned long rate = freq_table[index].frequency;
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unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000;
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int ret;
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/*
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* target freq == pll_p, don't need to take extra reference to pll_x_clk
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* as it isn't used anymore.
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*/
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if (rate == ifreq)
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return clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk);
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ret = clk_set_rate(cpufreq->pll_x_clk, rate * 1000);
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/* Restore to earlier frequency on error, i.e. pll_x */
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if (ret)
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dev_err(cpufreq->dev, "Failed to change pll_x to %lu\n", rate);
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ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_x_clk);
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/* This shouldn't fail while changing or restoring */
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WARN_ON(ret);
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/*
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* Drop count to pll_x clock only if we switched to intermediate freq
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* earlier while transitioning to a target frequency.
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*/
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if (cpufreq->pll_x_prepared) {
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clk_disable_unprepare(cpufreq->pll_x_clk);
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cpufreq->pll_x_prepared = false;
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}
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return ret;
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}
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static int tegra_cpu_init(struct cpufreq_policy *policy)
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{
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struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data();
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clk_prepare_enable(cpufreq->cpu_clk);
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/* FIXME: what's the actual transition time? */
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cpufreq_generic_init(policy, freq_table, 300 * 1000);
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policy->clk = cpufreq->cpu_clk;
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policy->suspend_freq = freq_table[0].frequency;
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return 0;
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}
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static int tegra_cpu_exit(struct cpufreq_policy *policy)
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{
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struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data();
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clk_disable_unprepare(cpufreq->cpu_clk);
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return 0;
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}
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static int tegra20_cpufreq_probe(struct platform_device *pdev)
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{
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struct tegra20_cpufreq *cpufreq;
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int err;
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cpufreq = devm_kzalloc(&pdev->dev, sizeof(*cpufreq), GFP_KERNEL);
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if (!cpufreq)
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return -ENOMEM;
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cpufreq->cpu_clk = clk_get_sys(NULL, "cclk");
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if (IS_ERR(cpufreq->cpu_clk))
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return PTR_ERR(cpufreq->cpu_clk);
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cpufreq->pll_x_clk = clk_get_sys(NULL, "pll_x");
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if (IS_ERR(cpufreq->pll_x_clk)) {
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err = PTR_ERR(cpufreq->pll_x_clk);
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goto put_cpu;
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}
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cpufreq->pll_p_clk = clk_get_sys(NULL, "pll_p");
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if (IS_ERR(cpufreq->pll_p_clk)) {
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err = PTR_ERR(cpufreq->pll_p_clk);
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goto put_pll_x;
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}
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cpufreq->dev = &pdev->dev;
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cpufreq->driver.get = cpufreq_generic_get;
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cpufreq->driver.attr = cpufreq_generic_attr;
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cpufreq->driver.init = tegra_cpu_init;
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cpufreq->driver.exit = tegra_cpu_exit;
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cpufreq->driver.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK;
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cpufreq->driver.verify = cpufreq_generic_frequency_table_verify;
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cpufreq->driver.suspend = cpufreq_generic_suspend;
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cpufreq->driver.driver_data = cpufreq;
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cpufreq->driver.target_index = tegra_target;
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cpufreq->driver.get_intermediate = tegra_get_intermediate;
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cpufreq->driver.target_intermediate = tegra_target_intermediate;
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snprintf(cpufreq->driver.name, CPUFREQ_NAME_LEN, "tegra");
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err = cpufreq_register_driver(&cpufreq->driver);
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if (err)
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goto put_pll_p;
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platform_set_drvdata(pdev, cpufreq);
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return 0;
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put_pll_p:
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clk_put(cpufreq->pll_p_clk);
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put_pll_x:
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clk_put(cpufreq->pll_x_clk);
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put_cpu:
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clk_put(cpufreq->cpu_clk);
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return err;
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}
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static int tegra20_cpufreq_remove(struct platform_device *pdev)
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{
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struct tegra20_cpufreq *cpufreq = platform_get_drvdata(pdev);
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cpufreq_unregister_driver(&cpufreq->driver);
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clk_put(cpufreq->pll_p_clk);
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clk_put(cpufreq->pll_x_clk);
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clk_put(cpufreq->cpu_clk);
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return 0;
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}
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static struct platform_driver tegra20_cpufreq_driver = {
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.probe = tegra20_cpufreq_probe,
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.remove = tegra20_cpufreq_remove,
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.driver = {
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.name = "tegra20-cpufreq",
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},
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};
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module_platform_driver(tegra20_cpufreq_driver);
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MODULE_ALIAS("platform:tegra20-cpufreq");
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MODULE_AUTHOR("Colin Cross <ccross@android.com>");
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MODULE_DESCRIPTION("NVIDIA Tegra20 cpufreq driver");
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MODULE_LICENSE("GPL");
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