mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 16:06:42 +07:00
a08fc7c805
The DSI controller needs a particular interface (CPU aka 8080) with some modifications from the TCON in order to run. Make sure the TCON is able to provide it when we are using the DSI output. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/129f5928113d2ca865bf5269047c2e4ba6fed5e6.1522835818.git-series.maxime.ripard@bootlin.com
283 lines
10 KiB
C
283 lines
10 KiB
C
/*
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* Copyright (C) 2015 Free Electrons
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* Copyright (C) 2015 NextThing Co
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*
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* Boris Brezillon <boris.brezillon@free-electrons.com>
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __SUN4I_TCON_H__
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#define __SUN4I_TCON_H__
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#include <drm/drm_crtc.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/reset.h>
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#define SUN4I_TCON_GCTL_REG 0x0
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#define SUN4I_TCON_GCTL_TCON_ENABLE BIT(31)
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#define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0)
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#define SUN4I_TCON_GCTL_IOMAP_TCON1 (1 << 0)
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#define SUN4I_TCON_GCTL_IOMAP_TCON0 (0 << 0)
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#define SUN4I_TCON_GINT0_REG 0x4
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#define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe) BIT(31 - (pipe))
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#define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE BIT(27)
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#define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_ENABLE BIT(26)
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#define SUN4I_TCON_GINT0_VBLANK_INT(pipe) BIT(15 - (pipe))
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#define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT BIT(11)
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#define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_INT BIT(10)
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#define SUN4I_TCON_GINT1_REG 0x8
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#define SUN4I_TCON_FRM_CTL_REG 0x10
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#define SUN4I_TCON_FRM_CTL_EN BIT(31)
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#define SUN4I_TCON_FRM_SEED_PR_REG 0x14
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#define SUN4I_TCON_FRM_SEED_PG_REG 0x18
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#define SUN4I_TCON_FRM_SEED_PB_REG 0x1c
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#define SUN4I_TCON_FRM_SEED_LR_REG 0x20
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#define SUN4I_TCON_FRM_SEED_LG_REG 0x24
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#define SUN4I_TCON_FRM_SEED_LB_REG 0x28
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#define SUN4I_TCON_FRM_TBL0_REG 0x2c
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#define SUN4I_TCON_FRM_TBL1_REG 0x30
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#define SUN4I_TCON_FRM_TBL2_REG 0x34
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#define SUN4I_TCON_FRM_TBL3_REG 0x38
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#define SUN4I_TCON0_CTL_REG 0x40
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#define SUN4I_TCON0_CTL_TCON_ENABLE BIT(31)
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#define SUN4I_TCON0_CTL_IF_MASK GENMASK(25, 24)
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#define SUN4I_TCON0_CTL_IF_8080 (1 << 24)
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#define SUN4I_TCON0_CTL_CLK_DELAY_MASK GENMASK(8, 4)
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#define SUN4I_TCON0_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK)
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#define SUN4I_TCON0_CTL_SRC_SEL_MASK GENMASK(2, 0)
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#define SUN4I_TCON0_DCLK_REG 0x44
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#define SUN4I_TCON0_DCLK_GATE_BIT (31)
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#define SUN4I_TCON0_DCLK_DIV_SHIFT (0)
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#define SUN4I_TCON0_DCLK_DIV_WIDTH (7)
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#define SUN4I_TCON0_BASIC0_REG 0x48
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#define SUN4I_TCON0_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16)
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#define SUN4I_TCON0_BASIC0_Y(height) (((height) - 1) & 0xfff)
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#define SUN4I_TCON0_BASIC1_REG 0x4c
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#define SUN4I_TCON0_BASIC1_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16)
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#define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp) (((bp) - 1) & 0xfff)
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#define SUN4I_TCON0_BASIC2_REG 0x50
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#define SUN4I_TCON0_BASIC2_V_TOTAL(total) (((total) & 0x1fff) << 16)
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#define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp) (((bp) - 1) & 0xfff)
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#define SUN4I_TCON0_BASIC3_REG 0x54
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#define SUN4I_TCON0_BASIC3_H_SYNC(width) ((((width) - 1) & 0x7ff) << 16)
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#define SUN4I_TCON0_BASIC3_V_SYNC(height) (((height) - 1) & 0x7ff)
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#define SUN4I_TCON0_HV_IF_REG 0x58
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#define SUN4I_TCON0_CPU_IF_REG 0x60
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#define SUN4I_TCON0_CPU_IF_MODE_MASK GENMASK(31, 28)
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#define SUN4I_TCON0_CPU_IF_MODE_DSI (1 << 28)
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#define SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH BIT(16)
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#define SUN4I_TCON0_CPU_IF_TRI_FIFO_EN BIT(2)
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#define SUN4I_TCON0_CPU_IF_TRI_EN BIT(0)
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#define SUN4I_TCON0_CPU_WR_REG 0x64
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#define SUN4I_TCON0_CPU_RD0_REG 0x68
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#define SUN4I_TCON0_CPU_RDA_REG 0x6c
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#define SUN4I_TCON0_TTL0_REG 0x70
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#define SUN4I_TCON0_TTL1_REG 0x74
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#define SUN4I_TCON0_TTL2_REG 0x78
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#define SUN4I_TCON0_TTL3_REG 0x7c
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#define SUN4I_TCON0_TTL4_REG 0x80
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#define SUN4I_TCON0_LVDS_IF_REG 0x84
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#define SUN4I_TCON0_LVDS_IF_EN BIT(31)
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#define SUN4I_TCON0_LVDS_IF_BITWIDTH_MASK BIT(26)
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#define SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS (1 << 26)
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#define SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS (0 << 26)
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#define SUN4I_TCON0_LVDS_IF_CLK_SEL_MASK BIT(20)
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#define SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 (1 << 20)
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#define SUN4I_TCON0_LVDS_IF_CLK_POL_MASK BIT(4)
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#define SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL (1 << 4)
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#define SUN4I_TCON0_LVDS_IF_CLK_POL_INV (0 << 4)
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#define SUN4I_TCON0_LVDS_IF_DATA_POL_MASK GENMASK(3, 0)
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#define SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL (0xf)
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#define SUN4I_TCON0_LVDS_IF_DATA_POL_INV (0)
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#define SUN4I_TCON0_IO_POL_REG 0x88
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#define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28)
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#define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25)
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#define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24)
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#define SUN4I_TCON0_IO_TRI_REG 0x8c
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#define SUN4I_TCON0_IO_TRI_HSYNC_DISABLE BIT(25)
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#define SUN4I_TCON0_IO_TRI_VSYNC_DISABLE BIT(24)
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#define SUN4I_TCON0_IO_TRI_DATA_PINS_DISABLE(pins) GENMASK(pins, 0)
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#define SUN4I_TCON1_CTL_REG 0x90
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#define SUN4I_TCON1_CTL_TCON_ENABLE BIT(31)
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#define SUN4I_TCON1_CTL_INTERLACE_ENABLE BIT(20)
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#define SUN4I_TCON1_CTL_CLK_DELAY_MASK GENMASK(8, 4)
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#define SUN4I_TCON1_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON1_CTL_CLK_DELAY_MASK)
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#define SUN4I_TCON1_CTL_SRC_SEL_MASK GENMASK(1, 0)
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#define SUN4I_TCON1_BASIC0_REG 0x94
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#define SUN4I_TCON1_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16)
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#define SUN4I_TCON1_BASIC0_Y(height) (((height) - 1) & 0xfff)
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#define SUN4I_TCON1_BASIC1_REG 0x98
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#define SUN4I_TCON1_BASIC1_X(width) ((((width) - 1) & 0xfff) << 16)
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#define SUN4I_TCON1_BASIC1_Y(height) (((height) - 1) & 0xfff)
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#define SUN4I_TCON1_BASIC2_REG 0x9c
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#define SUN4I_TCON1_BASIC2_X(width) ((((width) - 1) & 0xfff) << 16)
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#define SUN4I_TCON1_BASIC2_Y(height) (((height) - 1) & 0xfff)
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#define SUN4I_TCON1_BASIC3_REG 0xa0
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#define SUN4I_TCON1_BASIC3_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16)
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#define SUN4I_TCON1_BASIC3_H_BACKPORCH(bp) (((bp) - 1) & 0xfff)
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#define SUN4I_TCON1_BASIC4_REG 0xa4
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#define SUN4I_TCON1_BASIC4_V_TOTAL(total) (((total) & 0x1fff) << 16)
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#define SUN4I_TCON1_BASIC4_V_BACKPORCH(bp) (((bp) - 1) & 0xfff)
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#define SUN4I_TCON1_BASIC5_REG 0xa8
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#define SUN4I_TCON1_BASIC5_H_SYNC(width) ((((width) - 1) & 0x3ff) << 16)
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#define SUN4I_TCON1_BASIC5_V_SYNC(height) (((height) - 1) & 0x3ff)
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#define SUN4I_TCON1_IO_POL_REG 0xf0
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#define SUN4I_TCON1_IO_TRI_REG 0xf4
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#define SUN4I_TCON_ECC_FIFO_REG 0xf8
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#define SUN4I_TCON_ECC_FIFO_EN BIT(3)
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#define SUN4I_TCON_CEU_CTL_REG 0x100
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#define SUN4I_TCON_CEU_MUL_RR_REG 0x110
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#define SUN4I_TCON_CEU_MUL_RG_REG 0x114
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#define SUN4I_TCON_CEU_MUL_RB_REG 0x118
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#define SUN4I_TCON_CEU_ADD_RC_REG 0x11c
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#define SUN4I_TCON_CEU_MUL_GR_REG 0x120
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#define SUN4I_TCON_CEU_MUL_GG_REG 0x124
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#define SUN4I_TCON_CEU_MUL_GB_REG 0x128
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#define SUN4I_TCON_CEU_ADD_GC_REG 0x12c
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#define SUN4I_TCON_CEU_MUL_BR_REG 0x130
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#define SUN4I_TCON_CEU_MUL_BG_REG 0x134
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#define SUN4I_TCON_CEU_MUL_BB_REG 0x138
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#define SUN4I_TCON_CEU_ADD_BC_REG 0x13c
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#define SUN4I_TCON_CEU_RANGE_R_REG 0x140
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#define SUN4I_TCON_CEU_RANGE_G_REG 0x144
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#define SUN4I_TCON_CEU_RANGE_B_REG 0x148
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#define SUN4I_TCON0_CPU_TRI0_REG 0x160
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#define SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(space) ((((space) - 1) & 0xfff) << 16)
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#define SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(size) (((size) - 1) & 0xfff)
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#define SUN4I_TCON0_CPU_TRI1_REG 0x164
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#define SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(num) (((num) - 1) & 0xffff)
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#define SUN4I_TCON0_CPU_TRI2_REG 0x168
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#define SUN4I_TCON0_CPU_TRI2_START_DELAY(delay) (((delay) & 0xffff) << 16)
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#define SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(set) ((set) & 0xfff)
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#define SUN4I_TCON_SAFE_PERIOD_REG 0x1f0
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#define SUN4I_TCON_SAFE_PERIOD_NUM(num) (((num) & 0xfff) << 16)
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#define SUN4I_TCON_SAFE_PERIOD_MODE(mode) ((mode) & 0x3)
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#define SUN4I_TCON_MUX_CTRL_REG 0x200
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#define SUN4I_TCON0_LVDS_ANA0_REG 0x220
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#define SUN6I_TCON0_LVDS_ANA0_EN_MB BIT(31)
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#define SUN6I_TCON0_LVDS_ANA0_EN_LDO BIT(30)
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#define SUN6I_TCON0_LVDS_ANA0_EN_DRVC BIT(24)
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#define SUN6I_TCON0_LVDS_ANA0_EN_DRVD(x) (((x) & 0xf) << 20)
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#define SUN6I_TCON0_LVDS_ANA0_C(x) (((x) & 3) << 17)
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#define SUN6I_TCON0_LVDS_ANA0_V(x) (((x) & 3) << 8)
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#define SUN6I_TCON0_LVDS_ANA0_PD(x) (((x) & 3) << 4)
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#define SUN4I_TCON1_FILL_CTL_REG 0x300
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#define SUN4I_TCON1_FILL_BEG0_REG 0x304
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#define SUN4I_TCON1_FILL_END0_REG 0x308
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#define SUN4I_TCON1_FILL_DATA0_REG 0x30c
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#define SUN4I_TCON1_FILL_BEG1_REG 0x310
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#define SUN4I_TCON1_FILL_END1_REG 0x314
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#define SUN4I_TCON1_FILL_DATA1_REG 0x318
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#define SUN4I_TCON1_FILL_BEG2_REG 0x31c
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#define SUN4I_TCON1_FILL_END2_REG 0x320
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#define SUN4I_TCON1_FILL_DATA2_REG 0x324
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#define SUN4I_TCON1_GAMMA_TABLE_REG 0x400
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#define SUN4I_TCON_MAX_CHANNELS 2
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struct sun4i_tcon;
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struct sun4i_tcon_quirks {
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bool has_channel_0; /* a83t does not have channel 0 on second TCON */
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bool has_channel_1; /* a33 does not have channel 1 */
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bool has_lvds_alt; /* Does the LVDS clock have a parent other than the TCON clock? */
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bool needs_de_be_mux; /* sun6i needs mux to select backend */
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bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */
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bool supports_lvds; /* Does the TCON support an LVDS output? */
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/* callback to handle tcon muxing options */
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int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *);
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};
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struct sun4i_tcon {
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struct device *dev;
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struct drm_device *drm;
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struct regmap *regs;
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/* Main bus clock */
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struct clk *clk;
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/* Clocks for the TCON channels */
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struct clk *sclk0;
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struct clk *sclk1;
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/* Possible mux for the LVDS clock */
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struct clk *lvds_pll;
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/* Pixel clock */
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struct clk *dclk;
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u8 dclk_max_div;
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u8 dclk_min_div;
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/* Reset control */
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struct reset_control *lcd_rst;
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struct reset_control *lvds_rst;
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struct drm_panel *panel;
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/* Platform adjustments */
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const struct sun4i_tcon_quirks *quirks;
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/* Associated crtc */
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struct sun4i_crtc *crtc;
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int id;
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/* TCON list management */
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struct list_head list;
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};
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struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node);
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struct drm_panel *sun4i_tcon_find_panel(struct device_node *node);
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void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable);
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void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
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const struct drm_encoder *encoder,
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const struct drm_display_mode *mode);
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void sun4i_tcon_set_status(struct sun4i_tcon *crtc,
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const struct drm_encoder *encoder, bool enable);
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extern const struct of_device_id sun4i_tcon_of_table[];
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#endif /* __SUN4I_TCON_H__ */
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