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29746d0125
This patch adds decriptions for mt8183 IOMMU and SMI.
mt8183 has only one M4U like mt8173 and is also MTK IOMMU gen2 which
uses ARM Short-Descriptor translation table format.
The mt8183 M4U-SMI HW diagram is as below:
EMI
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M4U
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----------
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gals0-rx gals1-rx
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gals0-tx gals1-tx
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------------
SMI Common
------------
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+-----+-----+--------+-----+-----+-------+-------+
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| | gals-rx gals-rx | gals-rx gals-rx gals-rx
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| | gals-tx gals-tx | gals-tx gals-tx gals-tx
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larb0 larb1 IPU0 IPU1 larb4 larb5 larb6 CCU
disp vdec img cam venc img cam
All the connections are HW fixed, SW can NOT adjust it.
Compared with mt8173, we add a GALS(Global Async Local Sync) module
between SMI-common and M4U, and additional GALS between larb2/3/5/6
and SMI-common. GALS can help synchronize for the modules in different
clock frequency, it can be seen as a "asynchronous fifo".
GALS can only help transfer the command/data while it doesn't have
the configuring register, thus it has the special "smi" clock and it
doesn't have the "apb" clock. From the diagram above, we add "gals0"
and "gals1" clocks for smi-common and add a "gals" clock for smi-larb.
>From the diagram above, IPU0/IPU1(Image Processor Unit) and CCU(Camera
Control Unit) is connected with smi-common directly, we can take them
as "larb2", "larb3" and "larb7", and their register spaces are
different with the normal larb.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
102 lines
4.2 KiB
Plaintext
102 lines
4.2 KiB
Plaintext
* Mediatek IOMMU Architecture Implementation
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Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and
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this M4U have two generations of HW architecture. Generation one uses flat
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pagetable, and only supports 4K size page mapping. Generation two uses the
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ARM Short-Descriptor translation table format for address translation.
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About the M4U Hardware Block Diagram, please check below:
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EMI (External Memory Interface)
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m4u (Multimedia Memory Management Unit)
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+--------+
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gals0-rx gals1-rx (Global Async Local Sync rx)
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gals0-tx gals1-tx (Global Async Local Sync tx)
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| | Some SoCs may have GALS.
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+--------+
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SMI Common(Smart Multimedia Interface Common)
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+----------------+-------
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| gals-rx There may be GALS in some larbs.
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| gals-tx
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SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
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(display) (vdec)
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+-----+-----+ +----+----+
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| | |... | | | ... There are different ports in each larb.
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OVL0 RDMA0 WDMA0 MC PP VLD
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As above, The Multimedia HW will go through SMI and M4U while it
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access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
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smi local arbiter and smi common. It will control whether the Multimedia
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HW should go though the m4u for translation or bypass it and talk
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directly with EMI. And also SMI help control the power domain and clocks for
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each local arbiter.
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Normally we specify a local arbiter(larb) for each multimedia HW
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like display, video decode, and camera. And there are different ports
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in each larb. Take a example, There are many ports like MC, PP, VLD in the
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video decode local arbiter, all these ports are according to the video HW.
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In some SoCs, there may be a GALS(Global Async Local Sync) module between
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smi-common and m4u, and additional GALS module between smi-larb and
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smi-common. GALS can been seen as a "asynchronous fifo" which could help
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synchronize for the modules in different clock frequency.
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Required properties:
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- compatible : must be one of the following string:
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"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
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"mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
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"mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses
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generation one m4u HW.
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"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
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"mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW.
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- reg : m4u register base and size.
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- interrupts : the interrupt of m4u.
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- clocks : must contain one entry for each clock-names.
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- clock-names : Only 1 optional clock:
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- "bclk": the block clock of m4u.
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Here is the list which require this "bclk":
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- mt2701, mt2712, mt7623 and mt8173.
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Note that m4u use the EMI clock which always has been enabled before kernel
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if there is no this "bclk".
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- mediatek,larbs : List of phandle to the local arbiters in the current Socs.
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Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort
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according to the local arbiter index, like larb0, larb1, larb2...
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- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
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Specifies the mtk_m4u_id as defined in
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dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623
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dt-binding/memory/mt2712-larb-port.h for mt2712,
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dt-binding/memory/mt8173-larb-port.h for mt8173, and
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dt-binding/memory/mt8183-larb-port.h for mt8183.
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Example:
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iommu: iommu@10205000 {
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compatible = "mediatek,mt8173-m4u";
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reg = <0 0x10205000 0 0x1000>;
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interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_M4U>;
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clock-names = "bclk";
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mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>;
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#iommu-cells = <1>;
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};
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Example for a client device:
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display {
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compatible = "mediatek,mt8173-disp";
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iommus = <&iommu M4U_PORT_DISP_OVL0>,
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<&iommu M4U_PORT_DISP_RDMA0>;
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...
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};
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