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0f09870127
There are two eSDHC controllers in LS1012A. This patch is to add eSDHC nodes for ls1012a dts. Also enable eSDHC for RDB/QDS boards. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
451 lines
12 KiB
Plaintext
451 lines
12 KiB
Plaintext
/*
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* Device Tree Include file for Freescale Layerscape-1012A family SoC.
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*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPLv2 or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "fsl,ls1012a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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crypto = &crypto;
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rtic_a = &rtic_a;
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rtic_b = &rtic_b;
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rtic_c = &rtic_c;
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rtic_d = &rtic_d;
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sec_mon = &sec_mon;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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clocks = <&clockgen 1 0>;
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#cooling-cells = <2>;
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};
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};
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
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<1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
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<1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
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<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
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};
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gic: interrupt-controller@1400000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x1401000 0 0x1000>, /* GICD */
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<0x0 0x1402000 0 0x2000>, /* GICC */
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<0x0 0x1404000 0 0x2000>, /* GICH */
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<0x0 0x1406000 0 0x2000>; /* GICV */
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interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
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};
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reboot {
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compatible = "syscon-reboot";
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regmap = <&dcfg>;
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offset = <0xb0>;
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mask = <0x02>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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esdhc0: esdhc@1560000 {
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compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
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reg = <0x0 0x1560000 0x0 0x10000>;
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interrupts = <0 62 0x4>;
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clocks = <&clockgen 4 0>;
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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big-endian;
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bus-width = <4>;
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status = "disabled";
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};
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scfg: scfg@1570000 {
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compatible = "fsl,ls1012a-scfg", "syscon";
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reg = <0x0 0x1570000 0x0 0x10000>;
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big-endian;
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};
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esdhc1: esdhc@1580000 {
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compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
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reg = <0x0 0x1580000 0x0 0x10000>;
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interrupts = <0 65 0x4>;
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clocks = <&clockgen 4 0>;
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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big-endian;
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broken-cd;
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bus-width = <4>;
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status = "disabled";
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};
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crypto: crypto@1700000 {
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compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
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"fsl,sec-v4.0";
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fsl,sec-era = <8>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x1700000 0x100000>;
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reg = <0x00 0x1700000 0x0 0x100000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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sec_jr0: jr@10000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x10000 0x10000>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr1: jr@20000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x20000 0x10000>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr2: jr@30000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x30000 0x10000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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};
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sec_jr3: jr@40000 {
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compatible = "fsl,sec-v5.4-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x40000 0x10000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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};
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rtic@60000 {
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compatible = "fsl,sec-v5.4-rtic",
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"fsl,sec-v5.0-rtic",
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"fsl,sec-v4.0-rtic";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x60000 0x100 0x60e00 0x18>;
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ranges = <0x0 0x60100 0x500>;
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rtic_a: rtic-a@0 {
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compatible = "fsl,sec-v5.4-rtic-memory",
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"fsl,sec-v5.0-rtic-memory",
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"fsl,sec-v4.0-rtic-memory";
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reg = <0x00 0x20 0x100 0x100>;
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};
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rtic_b: rtic-b@20 {
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compatible = "fsl,sec-v5.4-rtic-memory",
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"fsl,sec-v5.0-rtic-memory",
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"fsl,sec-v4.0-rtic-memory";
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reg = <0x20 0x20 0x200 0x100>;
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};
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rtic_c: rtic-c@40 {
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compatible = "fsl,sec-v5.4-rtic-memory",
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"fsl,sec-v5.0-rtic-memory",
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"fsl,sec-v4.0-rtic-memory";
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reg = <0x40 0x20 0x300 0x100>;
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};
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rtic_d: rtic-d@60 {
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compatible = "fsl,sec-v5.4-rtic-memory",
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"fsl,sec-v5.0-rtic-memory",
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"fsl,sec-v4.0-rtic-memory";
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reg = <0x60 0x20 0x400 0x100>;
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};
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};
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};
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sec_mon: sec_mon@1e90000 {
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compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
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"fsl,sec-v4.0-mon";
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reg = <0x0 0x1e90000 0x0 0x10000>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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};
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dcfg: dcfg@1ee0000 {
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compatible = "fsl,ls1012a-dcfg",
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"syscon";
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reg = <0x0 0x1ee0000 0x0 0x10000>;
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big-endian;
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};
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clockgen: clocking@1ee1000 {
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compatible = "fsl,ls1012a-clockgen";
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reg = <0x0 0x1ee1000 0x0 0x1000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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tmu: tmu@1f00000 {
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compatible = "fsl,qoriq-tmu";
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reg = <0x0 0x1f00000 0x0 0x10000>;
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interrupts = <0 33 0x4>;
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fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
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fsl,tmu-calibration = <0x00000000 0x00000026
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0x00000001 0x0000002d
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0x00000002 0x00000032
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0x00000003 0x00000039
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0x00000004 0x0000003f
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0x00000005 0x00000046
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0x00000006 0x0000004d
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0x00000007 0x00000054
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0x00000008 0x0000005a
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0x00000009 0x00000061
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0x0000000a 0x0000006a
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0x0000000b 0x00000071
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0x00010000 0x00000025
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0x00010001 0x0000002c
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0x00010002 0x00000035
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0x00010003 0x0000003d
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0x00010004 0x00000045
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0x00010005 0x0000004e
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0x00010006 0x00000057
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0x00010007 0x00000061
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0x00010008 0x0000006b
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0x00010009 0x00000076
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0x00020000 0x00000029
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0x00020001 0x00000033
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0x00020002 0x0000003d
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0x00020003 0x00000049
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0x00020004 0x00000056
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0x00020005 0x00000061
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0x00020006 0x0000006d
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0x00030000 0x00000021
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0x00030001 0x0000002a
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0x00030002 0x0000003c
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0x00030003 0x0000004e>;
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big-endian;
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#thermal-sensor-cells = <1>;
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 0>;
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trips {
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cpu_alert: cpu-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu-crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT
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THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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i2c0: i2c@2180000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2180000 0x0 0x10000>;
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interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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i2c1: i2c@2190000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2190000 0x0 0x10000>;
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interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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duart0: serial@21c0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x00 0x21c0500 0x0 0x100>;
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interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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duart1: serial@21c0600 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x00 0x21c0600 0x0 0x100>;
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interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 0>;
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status = "disabled";
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};
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gpio0: gpio@2300000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2300000 0x0 0x10000>;
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interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@2310000 {
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compatible = "fsl,qoriq-gpio";
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reg = <0x0 0x2310000 0x0 0x10000>;
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interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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wdog0: wdog@2ad0000 {
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compatible = "fsl,ls1012a-wdt",
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"fsl,imx21-wdt";
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reg = <0x0 0x2ad0000 0x0 0x10000>;
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interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 0>;
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big-endian;
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};
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sai1: sai@2b50000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,vf610-sai";
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reg = <0x0 0x2b50000 0x0 0x10000>;
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interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 3>, <&clockgen 4 3>,
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<&clockgen 4 3>, <&clockgen 4 3>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dma-names = "tx", "rx";
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dmas = <&edma0 1 47>,
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<&edma0 1 46>;
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status = "disabled";
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};
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sai2: sai@2b60000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,vf610-sai";
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reg = <0x0 0x2b60000 0x0 0x10000>;
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 3>, <&clockgen 4 3>,
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<&clockgen 4 3>, <&clockgen 4 3>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dma-names = "tx", "rx";
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dmas = <&edma0 1 45>,
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<&edma0 1 44>;
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status = "disabled";
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};
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edma0: edma@2c00000 {
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#dma-cells = <2>;
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compatible = "fsl,vf610-edma";
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reg = <0x0 0x2c00000 0x0 0x10000>,
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<0x0 0x2c10000 0x0 0x10000>,
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<0x0 0x2c20000 0x0 0x10000>;
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interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
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<0 103 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma-tx", "edma-err";
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dma-channels = <32>;
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big-endian;
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clock-names = "dmamux0", "dmamux1";
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clocks = <&clockgen 4 3>,
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<&clockgen 4 3>;
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};
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sata: sata@3200000 {
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compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
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reg = <0x0 0x3200000 0x0 0x10000>,
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<0x0 0x20140520 0x0 0x4>;
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reg-names = "ahci", "sata-ecc";
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interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 0>;
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dma-coherent;
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status = "disabled";
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};
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};
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};
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