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Xilinx platforms have no hardwired video capture or video processing interface. Users create capture and memory to memory processing pipelines in the FPGA fabric to suit their particular needs, by instantiating video IP cores from a large library. The Xilinx Video IP core is a framework that models a video pipeline described in the device tree and expose the pipeline to userspace through the media controller and V4L2 APIs. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
110 lines
3.1 KiB
C
110 lines
3.1 KiB
C
/*
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* Xilinx Video DMA
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*
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* Copyright (C) 2013-2015 Ideas on Board
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* Copyright (C) 2013-2015 Xilinx, Inc.
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*
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* Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
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* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __XILINX_VIP_DMA_H__
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#define __XILINX_VIP_DMA_H__
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#include <linux/dmaengine.h>
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#include <linux/mutex.h>
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#include <linux/spinlock.h>
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#include <linux/videodev2.h>
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#include <media/media-entity.h>
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#include <media/v4l2-dev.h>
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#include <media/videobuf2-core.h>
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struct dma_chan;
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struct xvip_composite_device;
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struct xvip_video_format;
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/**
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* struct xvip_pipeline - Xilinx Video IP pipeline structure
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* @pipe: media pipeline
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* @lock: protects the pipeline @stream_count
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* @use_count: number of DMA engines using the pipeline
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* @stream_count: number of DMA engines currently streaming
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* @num_dmas: number of DMA engines in the pipeline
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* @output: DMA engine at the output of the pipeline
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*/
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struct xvip_pipeline {
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struct media_pipeline pipe;
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struct mutex lock;
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unsigned int use_count;
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unsigned int stream_count;
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unsigned int num_dmas;
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struct xvip_dma *output;
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};
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static inline struct xvip_pipeline *to_xvip_pipeline(struct media_entity *e)
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{
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return container_of(e->pipe, struct xvip_pipeline, pipe);
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}
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/**
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* struct xvip_dma - Video DMA channel
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* @list: list entry in a composite device dmas list
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* @video: V4L2 video device associated with the DMA channel
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* @pad: media pad for the video device entity
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* @xdev: composite device the DMA channel belongs to
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* @pipe: pipeline belonging to the DMA channel
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* @port: composite device DT node port number for the DMA channel
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* @lock: protects the @format, @fmtinfo and @queue fields
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* @format: active V4L2 pixel format
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* @fmtinfo: format information corresponding to the active @format
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* @queue: vb2 buffers queue
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* @alloc_ctx: allocation context for the vb2 @queue
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* @sequence: V4L2 buffers sequence number
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* @queued_bufs: list of queued buffers
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* @queued_lock: protects the buf_queued list
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* @dma: DMA engine channel
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* @align: transfer alignment required by the DMA channel (in bytes)
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* @xt: dma interleaved template for dma configuration
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* @sgl: data chunk structure for dma_interleaved_template
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*/
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struct xvip_dma {
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struct list_head list;
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struct video_device video;
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struct media_pad pad;
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struct xvip_composite_device *xdev;
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struct xvip_pipeline pipe;
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unsigned int port;
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struct mutex lock;
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struct v4l2_pix_format format;
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const struct xvip_video_format *fmtinfo;
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struct vb2_queue queue;
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void *alloc_ctx;
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unsigned int sequence;
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struct list_head queued_bufs;
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spinlock_t queued_lock;
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struct dma_chan *dma;
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unsigned int align;
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struct dma_interleaved_template xt;
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struct data_chunk sgl[1];
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};
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#define to_xvip_dma(vdev) container_of(vdev, struct xvip_dma, video)
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int xvip_dma_init(struct xvip_composite_device *xdev, struct xvip_dma *dma,
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enum v4l2_buf_type type, unsigned int port);
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void xvip_dma_cleanup(struct xvip_dma *dma);
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#endif /* __XILINX_VIP_DMA_H__ */
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