mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 12:56:49 +07:00
95e838c915
In some condition we receive the break interrupt but nothing is putted in the Rx FIFO and the correspondend bit in the status register is not set. Thus, no-one clear the interrupt and the handler will be called forever. This patch clear the break interrupt as soon as it occurs. Then, if the break character '\0' is putted in the fifo we will manage it. We can also unmask the Break interrupt but its bit in ISR is still set on break. So I think is better to keep the registers clean. Signed-off-by: Federico Vaga <federico.vaga@cern.ch> Acked-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
||
|---|---|---|
| .. | ||
| ipoctal.c | ||
| ipoctal.h | ||
| Kconfig | ||
| Makefile | ||
| scc2698.h | ||