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3f6d1767b1
The phy code was using implicit sequencing between the PHY driver and the UFS driver to implement certain hardware requirements. Specifically, the PHY reset register in the UFS controller needs to be deasserted before serdes start occurs in the PHY. Before this change, the code was doing this by utilizing the two phy callbacks, phy_init() and phy_poweron(), as "init step 1" and "init step 2", where the UFS driver would deassert reset between these two steps. This makes it challenging to power off the regulators in suspend, as regulators are initialized in init, not in poweron(), but only poweroff() is called during suspend, not exit(). For UFS, move the actual firing up of the PHY to phy_poweron() and phy_poweroff() callbacks, rather than init()/exit(). UFS calls phy_poweroff() during suspend, so now all clocks and regulators for the phy can be powered down during suspend. QMP is a little tricky because the PHY is also shared with PCIe and USB3, which have their own definitions for init() and poweron(). Rename the meaty functions to _enable() and _disable() to disentangle from the PHY core names, and then create two different ops structures: one for UFS and one for the other PHY types. In phy-qcom-ufs, remove the 'is_powered_on' and 'is_started' guards, as the generic PHY code does the reference counting. The 14/20nm-specific init functions get collapsed into the generic power_on() function, with the addition of a calibrate() callback specific to 14/20nm. Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
141 lines
4.2 KiB
C
141 lines
4.2 KiB
C
/*
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* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef UFS_QCOM_PHY_I_H_
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#define UFS_QCOM_PHY_I_H_
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/phy/phy.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#define UFS_QCOM_PHY_CAL_ENTRY(reg, val) \
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{ \
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.reg_offset = reg, \
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.cfg_value = val, \
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}
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#define UFS_QCOM_PHY_NAME_LEN 30
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enum {
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MASK_SERDES_START = 0x1,
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MASK_PCS_READY = 0x1,
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};
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enum {
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OFFSET_SERDES_START = 0x0,
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};
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struct ufs_qcom_phy_stored_attributes {
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u32 att;
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u32 value;
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};
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struct ufs_qcom_phy_calibration {
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u32 reg_offset;
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u32 cfg_value;
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};
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struct ufs_qcom_phy_vreg {
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const char *name;
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struct regulator *reg;
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int max_uA;
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int min_uV;
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int max_uV;
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bool enabled;
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};
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struct ufs_qcom_phy {
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struct list_head list;
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struct device *dev;
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void __iomem *mmio;
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void __iomem *dev_ref_clk_ctrl_mmio;
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struct clk *tx_iface_clk;
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struct clk *rx_iface_clk;
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bool is_iface_clk_enabled;
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struct clk *ref_clk_src;
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struct clk *ref_clk_parent;
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struct clk *ref_clk;
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bool is_ref_clk_enabled;
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bool is_dev_ref_clk_enabled;
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struct ufs_qcom_phy_vreg vdda_pll;
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struct ufs_qcom_phy_vreg vdda_phy;
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struct ufs_qcom_phy_vreg vddp_ref_clk;
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unsigned int quirks;
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/*
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* If UFS link is put into Hibern8 and if UFS PHY analog hardware is
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* power collapsed (by clearing UFS_PHY_POWER_DOWN_CONTROL), Hibern8
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* exit might fail even after powering on UFS PHY analog hardware.
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* Enabling this quirk will help to solve above issue by doing
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* custom PHY settings just before PHY analog power collapse.
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*/
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#define UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE BIT(0)
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u8 host_ctrl_rev_major;
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u16 host_ctrl_rev_minor;
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u16 host_ctrl_rev_step;
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char name[UFS_QCOM_PHY_NAME_LEN];
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struct ufs_qcom_phy_calibration *cached_regs;
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int cached_regs_table_size;
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struct ufs_qcom_phy_specific_ops *phy_spec_ops;
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enum phy_mode mode;
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struct reset_control *ufs_reset;
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};
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/**
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* struct ufs_qcom_phy_specific_ops - set of pointers to functions which have a
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* specific implementation per phy. Each UFS phy, should implement
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* those functions according to its spec and requirements
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* @start_serdes: pointer to a function that starts the serdes
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* @is_physical_coding_sublayer_ready: pointer to a function that
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* checks pcs readiness. returns 0 for success and non-zero for error.
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* @set_tx_lane_enable: pointer to a function that enable tx lanes
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* @power_control: pointer to a function that controls analog rail of phy
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* and writes to QSERDES_RX_SIGDET_CNTRL attribute
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*/
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struct ufs_qcom_phy_specific_ops {
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int (*calibrate)(struct ufs_qcom_phy *ufs_qcom_phy, bool is_rate_B);
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void (*start_serdes)(struct ufs_qcom_phy *phy);
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int (*is_physical_coding_sublayer_ready)(struct ufs_qcom_phy *phy);
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void (*set_tx_lane_enable)(struct ufs_qcom_phy *phy, u32 val);
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void (*power_control)(struct ufs_qcom_phy *phy, bool val);
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};
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struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy);
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int ufs_qcom_phy_power_on(struct phy *generic_phy);
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int ufs_qcom_phy_power_off(struct phy *generic_phy);
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int ufs_qcom_phy_init_clks(struct ufs_qcom_phy *phy_common);
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int ufs_qcom_phy_init_vregulators(struct ufs_qcom_phy *phy_common);
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int ufs_qcom_phy_remove(struct phy *generic_phy,
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struct ufs_qcom_phy *ufs_qcom_phy);
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struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
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struct ufs_qcom_phy *common_cfg,
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const struct phy_ops *ufs_qcom_phy_gen_ops,
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struct ufs_qcom_phy_specific_ops *phy_spec_ops);
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int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
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struct ufs_qcom_phy_calibration *tbl_A, int tbl_size_A,
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struct ufs_qcom_phy_calibration *tbl_B, int tbl_size_B,
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bool is_rate_B);
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#endif
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