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0672d22a19
Commit 6d4cd041f0 ("net: phy: at803x: disable delay only for RGMII mode")
exposed an issue on imx DTS files using AR8031/AR8035 PHYs.
The end result is that the boards can no longer obtain an IP address
via UDHCP, for example.
Quoting Andrew Lunn:
"The problem here is, all the DTs were broken since day 0. However,
because the PHY driver was also broken, nobody noticed and it
worked. Now that the PHY driver has been fixed, all the bugs in the
DTs now become an issue"
To fix this problem, the phy-mode property needs to be "rgmii-id", which
has the following meaning as per
Documentation/devicetree/bindings/net/ethernet.txt:
"RGMII with internal RX and TX delays provided by the PHY, the MAC should
not add the RX or TX delays in this case)"
Tested on imx6-sabresd, imx6sx-sdb and imx7d-pico boards with
successfully restored networking.
Based on the initial submission from Steve Twiss for the
imx6qdl-sabresd.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Tested-by: Soeren Moch <smoch@web.de>
Tested-by: Steve Twiss <stwiss.opensource@diasemi.com>
Tested-by: Adam Thomson <Adam.Thomson@diasemi.com>
Signed-off-by: Steve Twiss <stwiss.opensource@diasemi.com>
Tested-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
122 lines
4.3 KiB
Plaintext
122 lines
4.3 KiB
Plaintext
/*
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* Copyright (C) 2013,2014 Russell King
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/gpio/gpio.h>
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/ {
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vcc_3v3: regulator-vcc-3v3 {
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compatible = "regulator-fixed";
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regulator-always-on;
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regulator-name = "vcc_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
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phy-mode = "rgmii-id";
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phy-reset-duration = <2>;
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phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&iomuxc {
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microsom {
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pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
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fsl,pins = <
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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/* AR8035 reset */
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MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0
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/* AR8035 interrupt */
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MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
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/* GPIO16 -> AR8035 25MHz */
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MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0
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MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13030
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MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
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MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
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MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
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MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
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MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
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/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
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/* AR8035 pin strapping: IO voltage: pull up */
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MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
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/* AR8035 pin strapping: PHYADDR#0: pull down */
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MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
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/* AR8035 pin strapping: PHYADDR#1: pull down */
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MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
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/* AR8035 pin strapping: MODE#1: pull up */
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MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
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/* AR8035 pin strapping: MODE#3: pull up */
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MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
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/* AR8035 pin strapping: MODE#0: pull down */
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MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
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/*
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* As the RMII pins are also connected to RGMII
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* so that an AR8030 can be placed, set these
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* to high-z with the same pulls as above.
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* Use the GPIO settings to avoid changing the
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* input select registers.
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*/
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MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000
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MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000
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MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000
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>;
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};
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pinctrl_microsom_uart1: microsom-uart1 {
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fsl,pins = <
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MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
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MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
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>;
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};
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_microsom_uart1>;
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status = "okay";
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};
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