mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-14 05:06:41 +07:00
7e1c4e2792
When a memblock allocation APIs are called with align = 0, the alignment is implicitly set to SMP_CACHE_BYTES. Implicit alignment is done deep in the memblock allocator and it can come as a surprise. Not that such an alignment would be wrong even when used incorrectly but it is better to be explicit for the sake of clarity and the prinicple of the least surprise. Replace all such uses of memblock APIs with the 'align' parameter explicitly set to SMP_CACHE_BYTES and stop implicit alignment assignment in the memblock internal allocation functions. For the case when memblock APIs are used via helper functions, e.g. like iommu_arena_new_node() in Alpha, the helper functions were detected with Coccinelle's help and then manually examined and updated where appropriate. The direct memblock APIs users were updated using the semantic patch below: @@ expression size, min_addr, max_addr, nid; @@ ( | - memblock_alloc_try_nid_raw(size, 0, min_addr, max_addr, nid) + memblock_alloc_try_nid_raw(size, SMP_CACHE_BYTES, min_addr, max_addr, nid) | - memblock_alloc_try_nid_nopanic(size, 0, min_addr, max_addr, nid) + memblock_alloc_try_nid_nopanic(size, SMP_CACHE_BYTES, min_addr, max_addr, nid) | - memblock_alloc_try_nid(size, 0, min_addr, max_addr, nid) + memblock_alloc_try_nid(size, SMP_CACHE_BYTES, min_addr, max_addr, nid) | - memblock_alloc(size, 0) + memblock_alloc(size, SMP_CACHE_BYTES) | - memblock_alloc_raw(size, 0) + memblock_alloc_raw(size, SMP_CACHE_BYTES) | - memblock_alloc_from(size, 0, min_addr) + memblock_alloc_from(size, SMP_CACHE_BYTES, min_addr) | - memblock_alloc_nopanic(size, 0) + memblock_alloc_nopanic(size, SMP_CACHE_BYTES) | - memblock_alloc_low(size, 0) + memblock_alloc_low(size, SMP_CACHE_BYTES) | - memblock_alloc_low_nopanic(size, 0) + memblock_alloc_low_nopanic(size, SMP_CACHE_BYTES) | - memblock_alloc_from_nopanic(size, 0, min_addr) + memblock_alloc_from_nopanic(size, SMP_CACHE_BYTES, min_addr) | - memblock_alloc_node(size, 0, nid) + memblock_alloc_node(size, SMP_CACHE_BYTES, nid) ) [mhocko@suse.com: changelog update] [akpm@linux-foundation.org: coding-style fixes] [rppt@linux.ibm.com: fix missed uses of implicit alignment] Link: http://lkml.kernel.org/r/20181016133656.GA10925@rapoport-lnx Link: http://lkml.kernel.org/r/1538687224-17535-1-git-send-email-rppt@linux.vnet.ibm.com Signed-off-by: Mike Rapoport <rppt@linux.vnet.ibm.com> Suggested-by: Michal Hocko <mhocko@suse.com> Acked-by: Paul Burton <paul.burton@mips.com> [MIPS] Acked-by: Michael Ellerman <mpe@ellerman.id.au> [powerpc] Acked-by: Michal Hocko <mhocko@suse.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Zankel <chris@zankel.net> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Guan Xuetao <gxt@pku.edu.cn> Cc: Ingo Molnar <mingo@redhat.com> Cc: Matt Turner <mattst88@gmail.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Richard Weinberger <richard@nod.at> Cc: Russell King <linux@armlinux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
565 lines
13 KiB
C
565 lines
13 KiB
C
/*
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* TLB support routines.
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*
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* Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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*
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* 08/02/00 A. Mallick <asit.k.mallick@intel.com>
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* Modified RID allocation for SMP
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* Goutham Rao <goutham.rao@intel.com>
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* IPI based ptc implementation and A-step IPI implementation.
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* Rohit Seth <rohit.seth@intel.com>
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* Ken Chen <kenneth.w.chen@intel.com>
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* Christophe de Dinechin <ddd@hp.com>: Avoid ptc.e on memory allocation
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* Copyright (C) 2007 Intel Corp
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* Fenghua Yu <fenghua.yu@intel.com>
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* Add multiple ptc.g/ptc.ga instruction support in global tlb purge.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/mm.h>
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#include <linux/memblock.h>
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#include <linux/slab.h>
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#include <asm/delay.h>
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#include <asm/mmu_context.h>
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#include <asm/pgalloc.h>
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#include <asm/pal.h>
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#include <asm/tlbflush.h>
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#include <asm/dma.h>
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#include <asm/processor.h>
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#include <asm/sal.h>
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#include <asm/tlb.h>
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static struct {
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u64 mask; /* mask of supported purge page-sizes */
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unsigned long max_bits; /* log2 of largest supported purge page-size */
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} purge;
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struct ia64_ctx ia64_ctx = {
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.lock = __SPIN_LOCK_UNLOCKED(ia64_ctx.lock),
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.next = 1,
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.max_ctx = ~0U
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};
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DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
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DEFINE_PER_CPU(u8, ia64_tr_num); /*Number of TR slots in current processor*/
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DEFINE_PER_CPU(u8, ia64_tr_used); /*Max Slot number used by kernel*/
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struct ia64_tr_entry *ia64_idtrs[NR_CPUS];
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/*
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* Initializes the ia64_ctx.bitmap array based on max_ctx+1.
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* Called after cpu_init() has setup ia64_ctx.max_ctx based on
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* maximum RID that is supported by boot CPU.
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*/
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void __init
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mmu_context_init (void)
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{
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ia64_ctx.bitmap = memblock_alloc((ia64_ctx.max_ctx + 1) >> 3,
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SMP_CACHE_BYTES);
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ia64_ctx.flushmap = memblock_alloc((ia64_ctx.max_ctx + 1) >> 3,
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SMP_CACHE_BYTES);
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}
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/*
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* Acquire the ia64_ctx.lock before calling this function!
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*/
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void
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wrap_mmu_context (struct mm_struct *mm)
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{
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int i, cpu;
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unsigned long flush_bit;
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for (i=0; i <= ia64_ctx.max_ctx / BITS_PER_LONG; i++) {
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flush_bit = xchg(&ia64_ctx.flushmap[i], 0);
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ia64_ctx.bitmap[i] ^= flush_bit;
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}
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/* use offset at 300 to skip daemons */
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ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
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ia64_ctx.max_ctx, 300);
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ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
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ia64_ctx.max_ctx, ia64_ctx.next);
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/*
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* can't call flush_tlb_all() here because of race condition
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* with O(1) scheduler [EF]
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*/
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cpu = get_cpu(); /* prevent preemption/migration */
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for_each_online_cpu(i)
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if (i != cpu)
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per_cpu(ia64_need_tlb_flush, i) = 1;
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put_cpu();
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local_flush_tlb_all();
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}
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/*
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* Implement "spinaphores" ... like counting semaphores, but they
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* spin instead of sleeping. If there are ever any other users for
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* this primitive it can be moved up to a spinaphore.h header.
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*/
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struct spinaphore {
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unsigned long ticket;
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unsigned long serve;
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};
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static inline void spinaphore_init(struct spinaphore *ss, int val)
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{
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ss->ticket = 0;
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ss->serve = val;
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}
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static inline void down_spin(struct spinaphore *ss)
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{
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unsigned long t = ia64_fetchadd(1, &ss->ticket, acq), serve;
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if (time_before(t, ss->serve))
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return;
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ia64_invala();
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for (;;) {
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asm volatile ("ld8.c.nc %0=[%1]" : "=r"(serve) : "r"(&ss->serve) : "memory");
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if (time_before(t, serve))
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return;
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cpu_relax();
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}
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}
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static inline void up_spin(struct spinaphore *ss)
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{
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ia64_fetchadd(1, &ss->serve, rel);
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}
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static struct spinaphore ptcg_sem;
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static u16 nptcg = 1;
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static int need_ptcg_sem = 1;
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static int toolatetochangeptcgsem = 0;
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/*
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* Kernel parameter "nptcg=" overrides max number of concurrent global TLB
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* purges which is reported from either PAL or SAL PALO.
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*
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* We don't have sanity checking for nptcg value. It's the user's responsibility
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* for valid nptcg value on the platform. Otherwise, kernel may hang in some
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* cases.
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*/
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static int __init
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set_nptcg(char *str)
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{
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int value = 0;
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get_option(&str, &value);
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setup_ptcg_sem(value, NPTCG_FROM_KERNEL_PARAMETER);
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return 1;
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}
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__setup("nptcg=", set_nptcg);
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/*
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* Maximum number of simultaneous ptc.g purges in the system can
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* be defined by PAL_VM_SUMMARY (in which case we should take
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* the smallest value for any cpu in the system) or by the PAL
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* override table (in which case we should ignore the value from
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* PAL_VM_SUMMARY).
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*
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* Kernel parameter "nptcg=" overrides maximum number of simultanesous ptc.g
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* purges defined in either PAL_VM_SUMMARY or PAL override table. In this case,
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* we should ignore the value from either PAL_VM_SUMMARY or PAL override table.
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*
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* Complicating the logic here is the fact that num_possible_cpus()
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* isn't fully setup until we start bringing cpus online.
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*/
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void
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setup_ptcg_sem(int max_purges, int nptcg_from)
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{
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static int kp_override;
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static int palo_override;
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static int firstcpu = 1;
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if (toolatetochangeptcgsem) {
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if (nptcg_from == NPTCG_FROM_PAL && max_purges == 0)
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BUG_ON(1 < nptcg);
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else
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BUG_ON(max_purges < nptcg);
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return;
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}
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if (nptcg_from == NPTCG_FROM_KERNEL_PARAMETER) {
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kp_override = 1;
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nptcg = max_purges;
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goto resetsema;
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}
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if (kp_override) {
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need_ptcg_sem = num_possible_cpus() > nptcg;
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return;
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}
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if (nptcg_from == NPTCG_FROM_PALO) {
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palo_override = 1;
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/* In PALO max_purges == 0 really means it! */
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if (max_purges == 0)
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panic("Whoa! Platform does not support global TLB purges.\n");
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nptcg = max_purges;
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if (nptcg == PALO_MAX_TLB_PURGES) {
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need_ptcg_sem = 0;
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return;
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}
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goto resetsema;
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}
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if (palo_override) {
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if (nptcg != PALO_MAX_TLB_PURGES)
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need_ptcg_sem = (num_possible_cpus() > nptcg);
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return;
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}
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/* In PAL_VM_SUMMARY max_purges == 0 actually means 1 */
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if (max_purges == 0) max_purges = 1;
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if (firstcpu) {
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nptcg = max_purges;
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firstcpu = 0;
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}
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if (max_purges < nptcg)
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nptcg = max_purges;
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if (nptcg == PAL_MAX_PURGES) {
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need_ptcg_sem = 0;
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return;
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} else
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need_ptcg_sem = (num_possible_cpus() > nptcg);
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resetsema:
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spinaphore_init(&ptcg_sem, max_purges);
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}
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void
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ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
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unsigned long end, unsigned long nbits)
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{
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struct mm_struct *active_mm = current->active_mm;
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toolatetochangeptcgsem = 1;
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if (mm != active_mm) {
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/* Restore region IDs for mm */
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if (mm && active_mm) {
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activate_context(mm);
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} else {
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flush_tlb_all();
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return;
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}
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}
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if (need_ptcg_sem)
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down_spin(&ptcg_sem);
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do {
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/*
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* Flush ALAT entries also.
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*/
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ia64_ptcga(start, (nbits << 2));
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ia64_srlz_i();
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start += (1UL << nbits);
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} while (start < end);
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if (need_ptcg_sem)
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up_spin(&ptcg_sem);
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if (mm != active_mm) {
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activate_context(active_mm);
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}
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}
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void
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local_flush_tlb_all (void)
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{
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unsigned long i, j, flags, count0, count1, stride0, stride1, addr;
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addr = local_cpu_data->ptce_base;
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count0 = local_cpu_data->ptce_count[0];
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count1 = local_cpu_data->ptce_count[1];
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stride0 = local_cpu_data->ptce_stride[0];
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stride1 = local_cpu_data->ptce_stride[1];
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local_irq_save(flags);
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for (i = 0; i < count0; ++i) {
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for (j = 0; j < count1; ++j) {
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ia64_ptce(addr);
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addr += stride1;
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}
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addr += stride0;
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}
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local_irq_restore(flags);
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ia64_srlz_i(); /* srlz.i implies srlz.d */
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}
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void
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flush_tlb_range (struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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unsigned long size = end - start;
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unsigned long nbits;
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#ifndef CONFIG_SMP
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if (mm != current->active_mm) {
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mm->context = 0;
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return;
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}
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#endif
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nbits = ia64_fls(size + 0xfff);
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while (unlikely (((1UL << nbits) & purge.mask) == 0) &&
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(nbits < purge.max_bits))
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++nbits;
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if (nbits > purge.max_bits)
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nbits = purge.max_bits;
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start &= ~((1UL << nbits) - 1);
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preempt_disable();
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#ifdef CONFIG_SMP
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if (mm != current->active_mm || cpumask_weight(mm_cpumask(mm)) != 1) {
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platform_global_tlb_purge(mm, start, end, nbits);
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preempt_enable();
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return;
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}
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#endif
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do {
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ia64_ptcl(start, (nbits<<2));
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start += (1UL << nbits);
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} while (start < end);
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preempt_enable();
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ia64_srlz_i(); /* srlz.i implies srlz.d */
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}
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EXPORT_SYMBOL(flush_tlb_range);
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void ia64_tlb_init(void)
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{
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ia64_ptce_info_t uninitialized_var(ptce_info); /* GCC be quiet */
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u64 tr_pgbits;
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long status;
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pal_vm_info_1_u_t vm_info_1;
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pal_vm_info_2_u_t vm_info_2;
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int cpu = smp_processor_id();
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if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
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printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld; "
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"defaulting to architected purge page-sizes.\n", status);
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purge.mask = 0x115557000UL;
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}
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purge.max_bits = ia64_fls(purge.mask);
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ia64_get_ptce(&ptce_info);
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local_cpu_data->ptce_base = ptce_info.base;
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local_cpu_data->ptce_count[0] = ptce_info.count[0];
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local_cpu_data->ptce_count[1] = ptce_info.count[1];
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local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
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local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
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local_flush_tlb_all(); /* nuke left overs from bootstrapping... */
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status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2);
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if (status) {
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printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
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per_cpu(ia64_tr_num, cpu) = 8;
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return;
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}
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per_cpu(ia64_tr_num, cpu) = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
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if (per_cpu(ia64_tr_num, cpu) >
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(vm_info_1.pal_vm_info_1_s.max_dtr_entry+1))
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per_cpu(ia64_tr_num, cpu) =
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vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
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if (per_cpu(ia64_tr_num, cpu) > IA64_TR_ALLOC_MAX) {
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static int justonce = 1;
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per_cpu(ia64_tr_num, cpu) = IA64_TR_ALLOC_MAX;
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if (justonce) {
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justonce = 0;
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printk(KERN_DEBUG "TR register number exceeds "
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"IA64_TR_ALLOC_MAX!\n");
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}
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}
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}
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/*
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* is_tr_overlap
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*
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* Check overlap with inserted TRs.
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*/
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static int is_tr_overlap(struct ia64_tr_entry *p, u64 va, u64 log_size)
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{
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u64 tr_log_size;
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u64 tr_end;
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u64 va_rr = ia64_get_rr(va);
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u64 va_rid = RR_TO_RID(va_rr);
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u64 va_end = va + (1<<log_size) - 1;
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if (va_rid != RR_TO_RID(p->rr))
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return 0;
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tr_log_size = (p->itir & 0xff) >> 2;
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tr_end = p->ifa + (1<<tr_log_size) - 1;
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if (va > tr_end || p->ifa > va_end)
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return 0;
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return 1;
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}
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/*
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* ia64_insert_tr in virtual mode. Allocate a TR slot
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*
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* target_mask : 0x1 : itr, 0x2 : dtr, 0x3 : idtr
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*
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* va : virtual address.
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* pte : pte entries inserted.
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* log_size: range to be covered.
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*
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* Return value: <0 : error No.
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*
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* >=0 : slot number allocated for TR.
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* Must be called with preemption disabled.
|
|
*/
|
|
int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size)
|
|
{
|
|
int i, r;
|
|
unsigned long psr;
|
|
struct ia64_tr_entry *p;
|
|
int cpu = smp_processor_id();
|
|
|
|
if (!ia64_idtrs[cpu]) {
|
|
ia64_idtrs[cpu] = kmalloc_array(2 * IA64_TR_ALLOC_MAX,
|
|
sizeof(struct ia64_tr_entry),
|
|
GFP_KERNEL);
|
|
if (!ia64_idtrs[cpu])
|
|
return -ENOMEM;
|
|
}
|
|
r = -EINVAL;
|
|
/*Check overlap with existing TR entries*/
|
|
if (target_mask & 0x1) {
|
|
p = ia64_idtrs[cpu];
|
|
for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
|
|
i++, p++) {
|
|
if (p->pte & 0x1)
|
|
if (is_tr_overlap(p, va, log_size)) {
|
|
printk(KERN_DEBUG "Overlapped Entry"
|
|
"Inserted for TR Register!!\n");
|
|
goto out;
|
|
}
|
|
}
|
|
}
|
|
if (target_mask & 0x2) {
|
|
p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX;
|
|
for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
|
|
i++, p++) {
|
|
if (p->pte & 0x1)
|
|
if (is_tr_overlap(p, va, log_size)) {
|
|
printk(KERN_DEBUG "Overlapped Entry"
|
|
"Inserted for TR Register!!\n");
|
|
goto out;
|
|
}
|
|
}
|
|
}
|
|
|
|
for (i = IA64_TR_ALLOC_BASE; i < per_cpu(ia64_tr_num, cpu); i++) {
|
|
switch (target_mask & 0x3) {
|
|
case 1:
|
|
if (!((ia64_idtrs[cpu] + i)->pte & 0x1))
|
|
goto found;
|
|
continue;
|
|
case 2:
|
|
if (!((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
|
|
goto found;
|
|
continue;
|
|
case 3:
|
|
if (!((ia64_idtrs[cpu] + i)->pte & 0x1) &&
|
|
!((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
|
|
goto found;
|
|
continue;
|
|
default:
|
|
r = -EINVAL;
|
|
goto out;
|
|
}
|
|
}
|
|
found:
|
|
if (i >= per_cpu(ia64_tr_num, cpu))
|
|
return -EBUSY;
|
|
|
|
/*Record tr info for mca hander use!*/
|
|
if (i > per_cpu(ia64_tr_used, cpu))
|
|
per_cpu(ia64_tr_used, cpu) = i;
|
|
|
|
psr = ia64_clear_ic();
|
|
if (target_mask & 0x1) {
|
|
ia64_itr(0x1, i, va, pte, log_size);
|
|
ia64_srlz_i();
|
|
p = ia64_idtrs[cpu] + i;
|
|
p->ifa = va;
|
|
p->pte = pte;
|
|
p->itir = log_size << 2;
|
|
p->rr = ia64_get_rr(va);
|
|
}
|
|
if (target_mask & 0x2) {
|
|
ia64_itr(0x2, i, va, pte, log_size);
|
|
ia64_srlz_i();
|
|
p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i;
|
|
p->ifa = va;
|
|
p->pte = pte;
|
|
p->itir = log_size << 2;
|
|
p->rr = ia64_get_rr(va);
|
|
}
|
|
ia64_set_psr(psr);
|
|
r = i;
|
|
out:
|
|
return r;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ia64_itr_entry);
|
|
|
|
/*
|
|
* ia64_purge_tr
|
|
*
|
|
* target_mask: 0x1: purge itr, 0x2 : purge dtr, 0x3 purge idtr.
|
|
* slot: slot number to be freed.
|
|
*
|
|
* Must be called with preemption disabled.
|
|
*/
|
|
void ia64_ptr_entry(u64 target_mask, int slot)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
int i;
|
|
struct ia64_tr_entry *p;
|
|
|
|
if (slot < IA64_TR_ALLOC_BASE || slot >= per_cpu(ia64_tr_num, cpu))
|
|
return;
|
|
|
|
if (target_mask & 0x1) {
|
|
p = ia64_idtrs[cpu] + slot;
|
|
if ((p->pte&0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
|
|
p->pte = 0;
|
|
ia64_ptr(0x1, p->ifa, p->itir>>2);
|
|
ia64_srlz_i();
|
|
}
|
|
}
|
|
|
|
if (target_mask & 0x2) {
|
|
p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + slot;
|
|
if ((p->pte & 0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
|
|
p->pte = 0;
|
|
ia64_ptr(0x2, p->ifa, p->itir>>2);
|
|
ia64_srlz_i();
|
|
}
|
|
}
|
|
|
|
for (i = per_cpu(ia64_tr_used, cpu); i >= IA64_TR_ALLOC_BASE; i--) {
|
|
if (((ia64_idtrs[cpu] + i)->pte & 0x1) ||
|
|
((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
|
|
break;
|
|
}
|
|
per_cpu(ia64_tr_used, cpu) = i;
|
|
}
|
|
EXPORT_SYMBOL_GPL(ia64_ptr_entry);
|