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Aurora is a L2 Cache Controller designed to be compatible with the L2x0 Cache Controller. L2X0 OF bindings are extended to support some specificity of Aurora (no cache id part number available through hardware, always write through mode, choice between outer cache and system cache). Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Tested-and-reviewed-by: Lior Amsalem <alior@marvell.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Barry Song <21cnbao@gmail.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
54 lines
2.1 KiB
Plaintext
54 lines
2.1 KiB
Plaintext
* ARM L2 Cache Controller
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ARM cores often have a separate level 2 cache controller. There are various
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implementations of the L2 cache controller with compatible programming models.
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The ARM L2 cache representation in the device tree should be done as follows:
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Required properties:
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- compatible : should be one of:
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"arm,pl310-cache"
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"arm,l220-cache"
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"arm,l210-cache"
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"marvell,aurora-system-cache": Marvell Controller designed to be
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compatible with the ARM one, with system cache mode (meaning
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maintenance operations on L1 are broadcasted to the L2 and L2
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performs the same operation).
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"marvell,"aurora-outer-cache: Marvell Controller designed to be
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compatible with the ARM one with outer cache mode.
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- cache-unified : Specifies the cache is a unified cache.
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- cache-level : Should be set to 2 for a level 2 cache.
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- reg : Physical base address and size of cache controller's memory mapped
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registers.
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Optional properties:
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- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
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read, write and setup latencies. Minimum valid values are 1. Controllers
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without setup latency control should use a value of 0.
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- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
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read, write and setup latencies. Controllers without setup latency control
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should use 0. Controllers without separate read and write Tag RAM latency
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values should only use the first cell.
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- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
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- arm,filter-ranges : <start length> Starting address and length of window to
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filter. Addresses in the filter window are directed to the M1 port. Other
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addresses will go to the M0 port.
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- interrupts : 1 combined interrupt.
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- cache-id-part: cache id part number to be used if it is not present
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on hardware
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- wt-override: If present then L2 is forced to Write through mode
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Example:
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L2: cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0xfff12000 0x1000>;
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arm,data-latency = <1 1 1>;
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arm,tag-latency = <2 2 2>;
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arm,filter-latency = <0x80000000 0x8000000>;
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cache-unified;
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cache-level = <2>;
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interrupts = <45>;
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};
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