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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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73c1b41e63
When the state names got added a script was used to add the extra argument to the calls. The script basically converted the state constant to a string, but the cleanup to convert these strings into meaningful ones did not happen. Replace all the useless strings with 'subsys/xxx/yyy:state' strings which are used in all the other places already. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sebastian Siewior <bigeasy@linutronix.de> Link: http://lkml.kernel.org/r/20161221192112.085444152@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
306 lines
8.0 KiB
C
306 lines
8.0 KiB
C
/*
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* Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
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* platforms.
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*
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* Copyright (C) 2012 Marvell
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*
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* Yehuda Yitschak <yehuday@marvell.com>
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* Gregory Clement <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
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* responsible for ensuring hardware coherency between all CPUs and between
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* CPUs and I/O masters. This file initializes the coherency fabric and
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* supplies basic routines for configuring and controlling hardware coherency
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*/
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#define pr_fmt(fmt) "mvebu-coherency: " fmt
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/smp.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/mbus.h>
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#include <linux/pci.h>
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#include <asm/smp_plat.h>
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#include <asm/cacheflush.h>
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#include <asm/mach/map.h>
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#include <asm/dma-mapping.h>
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#include "coherency.h"
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#include "mvebu-soc-id.h"
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unsigned long coherency_phys_base;
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void __iomem *coherency_base;
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static void __iomem *coherency_cpu_base;
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static void __iomem *cpu_config_base;
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/* Coherency fabric registers */
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#define IO_SYNC_BARRIER_CTL_OFFSET 0x0
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enum {
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COHERENCY_FABRIC_TYPE_NONE,
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COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
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COHERENCY_FABRIC_TYPE_ARMADA_375,
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COHERENCY_FABRIC_TYPE_ARMADA_380,
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};
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static const struct of_device_id of_coherency_table[] = {
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{.compatible = "marvell,coherency-fabric",
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.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
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{.compatible = "marvell,armada-375-coherency-fabric",
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.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 },
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{.compatible = "marvell,armada-380-coherency-fabric",
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.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 },
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{ /* end of list */ },
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};
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/* Functions defined in coherency_ll.S */
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int ll_enable_coherency(void);
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void ll_add_cpu_to_smp_group(void);
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#define CPU_CONFIG_SHARED_L2 BIT(16)
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/*
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* Disable the "Shared L2 Present" bit in CPU Configuration register
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* on Armada XP.
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*
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* The "Shared L2 Present" bit affects the "level of coherence" value
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* in the clidr CP15 register. Cache operation functions such as
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* "flush all" and "invalidate all" operate on all the cache levels
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* that included in the defined level of coherence. When HW I/O
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* coherency is used, this bit causes unnecessary flushes of the L2
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* cache.
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*/
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static void armada_xp_clear_shared_l2(void)
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{
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u32 reg;
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if (!cpu_config_base)
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return;
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reg = readl(cpu_config_base);
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reg &= ~CPU_CONFIG_SHARED_L2;
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writel(reg, cpu_config_base);
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}
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static int mvebu_hwcc_notifier(struct notifier_block *nb,
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unsigned long event, void *__dev)
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{
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struct device *dev = __dev;
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if (event != BUS_NOTIFY_ADD_DEVICE)
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return NOTIFY_DONE;
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set_dma_ops(dev, &arm_coherent_dma_ops);
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return NOTIFY_OK;
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}
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static struct notifier_block mvebu_hwcc_nb = {
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.notifier_call = mvebu_hwcc_notifier,
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};
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static struct notifier_block mvebu_hwcc_pci_nb __maybe_unused = {
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.notifier_call = mvebu_hwcc_notifier,
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};
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static int armada_xp_clear_l2_starting(unsigned int cpu)
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{
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armada_xp_clear_shared_l2();
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return 0;
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}
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static void __init armada_370_coherency_init(struct device_node *np)
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{
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struct resource res;
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struct device_node *cpu_config_np;
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of_address_to_resource(np, 0, &res);
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coherency_phys_base = res.start;
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/*
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* Ensure secondary CPUs will see the updated value,
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* which they read before they join the coherency
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* fabric, and therefore before they are coherent with
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* the boot CPU cache.
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*/
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sync_cache_w(&coherency_phys_base);
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coherency_base = of_iomap(np, 0);
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coherency_cpu_base = of_iomap(np, 1);
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cpu_config_np = of_find_compatible_node(NULL, NULL,
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"marvell,armada-xp-cpu-config");
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if (!cpu_config_np)
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goto exit;
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cpu_config_base = of_iomap(cpu_config_np, 0);
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if (!cpu_config_base) {
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of_node_put(cpu_config_np);
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goto exit;
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}
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of_node_put(cpu_config_np);
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cpuhp_setup_state_nocalls(CPUHP_AP_ARM_MVEBU_COHERENCY,
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"arm/mvebu/coherency:starting",
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armada_xp_clear_l2_starting, NULL);
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exit:
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set_cpu_coherent();
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}
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/*
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* This ioremap hook is used on Armada 375/38x to ensure that all MMIO
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* areas are mapped as MT_UNCACHED instead of MT_DEVICE. This is
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* needed for the HW I/O coherency mechanism to work properly without
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* deadlock.
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*/
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static void __iomem *
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armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
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unsigned int mtype, void *caller)
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{
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mtype = MT_UNCACHED;
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return __arm_ioremap_caller(phys_addr, size, mtype, caller);
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}
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static void __init armada_375_380_coherency_init(struct device_node *np)
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{
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struct device_node *cache_dn;
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coherency_cpu_base = of_iomap(np, 0);
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arch_ioremap_caller = armada_wa_ioremap_caller;
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pci_ioremap_set_mem_type(MT_UNCACHED);
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/*
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* We should switch the PL310 to I/O coherency mode only if
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* I/O coherency is actually enabled.
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*/
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if (!coherency_available())
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return;
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/*
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* Add the PL310 property "arm,io-coherent". This makes sure the
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* outer sync operation is not used, which allows to
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* workaround the system erratum that causes deadlocks when
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* doing PCIe in an SMP situation on Armada 375 and Armada
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* 38x.
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*/
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for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
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struct property *p;
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p = kzalloc(sizeof(*p), GFP_KERNEL);
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p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
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of_add_property(cache_dn, p);
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}
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}
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static int coherency_type(void)
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{
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struct device_node *np;
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const struct of_device_id *match;
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int type;
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/*
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* The coherency fabric is needed:
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* - For coherency between processors on Armada XP, so only
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* when SMP is enabled.
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* - For coherency between the processor and I/O devices, but
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* this coherency requires many pre-requisites (write
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* allocate cache policy, shareable pages, SMP bit set) that
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* are only meant in SMP situations.
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*
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* Note that this means that on Armada 370, there is currently
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* no way to use hardware I/O coherency, because even when
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* CONFIG_SMP is enabled, is_smp() returns false due to the
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* Armada 370 being a single-core processor. To lift this
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* limitation, we would have to find a way to make the cache
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* policy set to write-allocate (on all Armada SoCs), and to
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* set the shareable attribute in page tables (on all Armada
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* SoCs except the Armada 370). Unfortunately, such decisions
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* are taken very early in the kernel boot process, at a point
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* where we don't know yet on which SoC we are running.
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*/
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if (!is_smp())
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return COHERENCY_FABRIC_TYPE_NONE;
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np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
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if (!np)
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return COHERENCY_FABRIC_TYPE_NONE;
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type = (int) match->data;
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of_node_put(np);
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return type;
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}
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int set_cpu_coherent(void)
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{
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int type = coherency_type();
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if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) {
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if (!coherency_base) {
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pr_warn("Can't make current CPU cache coherent.\n");
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pr_warn("Coherency fabric is not initialized\n");
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return 1;
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}
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armada_xp_clear_shared_l2();
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ll_add_cpu_to_smp_group();
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return ll_enable_coherency();
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}
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return 0;
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}
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int coherency_available(void)
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{
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return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
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}
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int __init coherency_init(void)
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{
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int type = coherency_type();
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struct device_node *np;
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np = of_find_matching_node(NULL, of_coherency_table);
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if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
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armada_370_coherency_init(np);
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else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 ||
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type == COHERENCY_FABRIC_TYPE_ARMADA_380)
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armada_375_380_coherency_init(np);
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of_node_put(np);
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return 0;
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}
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static int __init coherency_late_init(void)
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{
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if (coherency_available())
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bus_register_notifier(&platform_bus_type,
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&mvebu_hwcc_nb);
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return 0;
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}
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postcore_initcall(coherency_late_init);
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#if IS_ENABLED(CONFIG_PCI)
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static int __init coherency_pci_init(void)
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{
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if (coherency_available())
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bus_register_notifier(&pci_bus_type,
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&mvebu_hwcc_pci_nb);
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return 0;
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}
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arch_initcall(coherency_pci_init);
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#endif
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