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d8e8fd0ebf
Currently, this driver sticks to the legacy NAND model because it was
upstreamed before commit 2d472aba15 ("mtd: nand: document the NAND
controller/NAND chip DT representation"). However, relying on the
dummy_controller is already deprecated.
Switch over to the new controller/chip representation.
The struct denali_nand_info has been split into denali_controller
and denali_chip, to contain the controller data, per-chip data,
respectively.
One problem is, this commit changes the DT binding. So, as always,
the backward compatibility must be taken into consideration.
In the new binding, the controller node expects
#address-cells = <1>;
#size-cells = <0>;
... since the child nodes represent NAND chips.
In the old binding, the controller node may have subnodes, but they
are MTD partitions.
The denali_dt_is_legacy_binding() exploits it to distinguish old/new
platforms.
Going forward, the old binding is only allowed for existing DT files.
I updated the binding document.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
55 lines
2.0 KiB
Plaintext
55 lines
2.0 KiB
Plaintext
* Denali NAND controller
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Required properties:
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- compatible : should be one of the following:
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"altr,socfpga-denali-nand" - for Altera SOCFPGA
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"socionext,uniphier-denali-nand-v5a" - for Socionext UniPhier (v5a)
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"socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b)
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- reg : should contain registers location and length for data and reg.
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- reg-names: Should contain the reg names "nand_data" and "denali_reg"
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- #address-cells: should be 1. The cell encodes the chip select connection.
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- #size-cells : should be 0.
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- interrupts : The interrupt number.
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- clocks: should contain phandle of the controller core clock, the bus
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interface clock, and the ECC circuit clock.
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- clock-names: should contain "nand", "nand_x", "ecc"
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Sub-nodes:
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Sub-nodes represent available NAND chips.
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Required properties:
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- reg: should contain the bank ID of the controller to which each chip
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select is connected.
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Optional properties:
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- nand-ecc-step-size: see nand.txt for details.
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If present, the value must be
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512 for "altr,socfpga-denali-nand"
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1024 for "socionext,uniphier-denali-nand-v5a"
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1024 for "socionext,uniphier-denali-nand-v5b"
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- nand-ecc-strength: see nand.txt for details. Valid values are:
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8, 15 for "altr,socfpga-denali-nand"
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8, 16, 24 for "socionext,uniphier-denali-nand-v5a"
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8, 16 for "socionext,uniphier-denali-nand-v5b"
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- nand-ecc-maximize: see nand.txt for details
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The chip nodes may optionally contain sub-nodes describing partitions of the
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address space. See partition.txt for more detail.
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Examples:
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nand: nand@ff900000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "altr,socfpga-denali-nand";
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reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
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reg-names = "nand_data", "denali_reg";
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clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
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clock-names = "nand", "nand_x", "ecc";
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interrupts = <0 144 4>;
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nand@0 {
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reg = <0>;
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}
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};
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