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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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73e990b424
MediaTek platform and UFS controller can dynamically customize the delay for host enabling according to different scenarios. For example, if UniPro enters lower-power mode, such delay can be minimized, otherwise longer delay shall be expected. Link: https://lore.kernel.org/r/20200318104016.28049-8-stanley.chu@mediatek.com Reviewed-by: Avri Altman <avri.altman@wdc.com> Signed-off-by: Stanley Chu <stanley.chu@mediatek.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
101 lines
2.3 KiB
C
101 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 MediaTek Inc.
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*/
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#ifndef _UFS_MEDIATEK_H
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#define _UFS_MEDIATEK_H
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#include <linux/bitops.h>
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#include <linux/soc/mediatek/mtk_sip_svc.h>
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/*
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* Vendor specific UFSHCI Registers
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*/
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#define REG_UFS_REFCLK_CTRL 0x144
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#define REG_UFS_EXTREG 0x2100
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#define REG_UFS_MPHYCTRL 0x2200
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#define REG_UFS_REJECT_MON 0x22AC
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#define REG_UFS_DEBUG_SEL 0x22C0
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#define REG_UFS_PROBE 0x22C8
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/*
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* Ref-clk control
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*
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* Values for register REG_UFS_REFCLK_CTRL
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*/
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#define REFCLK_RELEASE 0x0
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#define REFCLK_REQUEST BIT(0)
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#define REFCLK_ACK BIT(1)
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#define REFCLK_REQ_TIMEOUT_MS 3
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/*
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* Vendor specific pre-defined parameters
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*/
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#define UFS_MTK_LIMIT_NUM_LANES_RX 1
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#define UFS_MTK_LIMIT_NUM_LANES_TX 1
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#define UFS_MTK_LIMIT_HSGEAR_RX UFS_HS_G3
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#define UFS_MTK_LIMIT_HSGEAR_TX UFS_HS_G3
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#define UFS_MTK_LIMIT_PWMGEAR_RX UFS_PWM_G4
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#define UFS_MTK_LIMIT_PWMGEAR_TX UFS_PWM_G4
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#define UFS_MTK_LIMIT_RX_PWR_PWM SLOW_MODE
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#define UFS_MTK_LIMIT_TX_PWR_PWM SLOW_MODE
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#define UFS_MTK_LIMIT_RX_PWR_HS FAST_MODE
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#define UFS_MTK_LIMIT_TX_PWR_HS FAST_MODE
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#define UFS_MTK_LIMIT_HS_RATE PA_HS_MODE_B
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#define UFS_MTK_LIMIT_DESIRED_MODE UFS_HS_MODE
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/*
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* Other attributes
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*/
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#define VS_DEBUGCLOCKENABLE 0xD0A1
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#define VS_SAVEPOWERCONTROL 0xD0A6
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#define VS_UNIPROPOWERDOWNCONTROL 0xD0A8
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/*
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* Vendor specific link state
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*/
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enum {
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VS_LINK_DISABLED = 0,
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VS_LINK_DOWN = 1,
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VS_LINK_UP = 2,
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VS_LINK_HIBERN8 = 3,
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VS_LINK_LOST = 4,
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VS_LINK_CFG = 5,
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};
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/*
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* SiP commands
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*/
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#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276)
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#define UFS_MTK_SIP_DEVICE_RESET BIT(1)
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#define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3)
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/*
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* VS_DEBUGCLOCKENABLE
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*/
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enum {
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TX_SYMBOL_CLK_REQ_FORCE = 5,
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};
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/*
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* VS_SAVEPOWERCONTROL
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*/
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enum {
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RX_SYMBOL_CLK_GATE_EN = 0,
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SYS_CLK_GATE_EN = 2,
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TX_CLK_GATE_EN = 3,
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};
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struct ufs_mtk_host {
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struct ufs_hba *hba;
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struct phy *mphy;
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bool unipro_lpm;
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bool ref_clk_enabled;
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u16 ref_clk_ungating_wait_us;
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u16 ref_clk_gating_wait_us;
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};
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#endif /* !_UFS_MEDIATEK_H */
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