mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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00a9730e10
This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
80 lines
1.9 KiB
C
80 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/spinlock.h>
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#include <linux/smp.h>
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#include <asm/cache.h>
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#include <asm/barrier.h>
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inline void dcache_wb_line(unsigned long start)
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{
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asm volatile("dcache.cval1 %0\n"::"r"(start):"memory");
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sync_is();
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}
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void icache_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("icache.iva %0\n"::"r"(i):"memory");
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sync_is();
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}
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void icache_inv_all(void)
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{
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asm volatile("icache.ialls\n":::"memory");
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sync_is();
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}
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void dcache_wb_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.cval1 %0\n"::"r"(i):"memory");
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sync_is();
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}
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void dcache_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.civa %0\n"::"r"(i):"memory");
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sync_is();
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}
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void cache_wbinv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.cval1 %0\n"::"r"(i):"memory");
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sync_is();
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i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("icache.iva %0\n"::"r"(i):"memory");
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sync_is();
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}
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EXPORT_SYMBOL(cache_wbinv_range);
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void dma_wbinv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.civa %0\n"::"r"(i):"memory");
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sync_is();
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}
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void dma_wb_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.civa %0\n"::"r"(i):"memory");
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sync_is();
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}
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