Alex Deucher 3e10f3196b drm/amdgpu/display: switch udelay to msleep ... We may need to sleep for up to 80ms (8ms per each of up to 10 loop iterations): /* First DPCD read after VDD ON can fail if the particular board * does not have HPD pin wired correctly. So if DPCD read fails, * which it should never happen, retry a few times. Target worst * case scenario of 80 ms. */ Switch udelay to msleep to avoid limits on arm. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-06-25 12:08:46 -05:00
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acp	treewide: Add SPDX license identifier - Makefile/Kconfig	2019-05-21 10:50:46 +02:00
amdgpu	Merge branch 'drm-next' into drm-next-5.3	2019-06-25 08:42:25 -05:00
amdkfd	drm/amdkfd: Set gws_mask to 64 bit 1s	2019-06-22 09:34:14 -05:00
display	drm/amdgpu/display: switch udelay to msleep	2019-06-25 12:08:46 -05:00
include	drm/amd/display: Create DWB resource for DCN2	2019-06-22 09:34:11 -05:00
powerplay	drm/amdgpu/powerplay: FEATURE_MASK is 64 bit so use ULL	2019-06-25 12:08:19 -05:00