mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
33f92a8a92
The field PLLDIVVALUE of register PHY_CTRL_1 selects the reference clock source for the PHY: 00 = sysclock uses 19.2 MHz 01 = sysclock uses 24 MHz 10 = sysclock uses 26 MHz 11 = sysclock uses 27 MHz The reset value for this field is 10 according to the reference manual, and even though this reset value works for mx53, it does not work for mx51. So instead of relying on the reset value for the PLLDIVVALUE field, explicitly set it to 01 so that a 24MHz clock can be selected for the PHY and allowing both mx51 and mx53 to have USB OTG port functional. Succesfully tested 'g_ether' on a imx51-babbage and on a imx53-qsb boards. Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
356 lines
8.2 KiB
C
356 lines
8.2 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include "ci_hdrc_imx.h"
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#define MX25_USB_PHY_CTRL_OFFSET 0x08
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#define MX25_BM_EXTERNAL_VBUS_DIVIDER BIT(23)
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#define MX25_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
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#define MX25_EHCI_INTERFACE_DIFF_UNI (0 << 0)
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#define MX25_EHCI_INTERFACE_MASK (0xf)
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#define MX25_OTG_SIC_SHIFT 29
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#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
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#define MX25_OTG_PM_BIT BIT(24)
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#define MX25_OTG_PP_BIT BIT(11)
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#define MX25_OTG_OCPOL_BIT BIT(3)
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#define MX25_H1_SIC_SHIFT 21
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#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
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#define MX25_H1_PP_BIT BIT(18)
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#define MX25_H1_PM_BIT BIT(16)
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#define MX25_H1_IPPUE_UP_BIT BIT(7)
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#define MX25_H1_IPPUE_DOWN_BIT BIT(6)
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#define MX25_H1_TLL_BIT BIT(5)
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#define MX25_H1_USBTE_BIT BIT(4)
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#define MX25_H1_OCPOL_BIT BIT(2)
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#define MX27_H1_PM_BIT BIT(8)
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#define MX27_H2_PM_BIT BIT(16)
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#define MX27_OTG_PM_BIT BIT(24)
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#define MX53_USB_OTG_PHY_CTRL_0_OFFSET 0x08
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#define MX53_USB_OTG_PHY_CTRL_1_OFFSET 0x0c
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#define MX53_USB_UH2_CTRL_OFFSET 0x14
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#define MX53_USB_UH3_CTRL_OFFSET 0x18
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#define MX53_BM_OVER_CUR_DIS_H1 BIT(5)
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#define MX53_BM_OVER_CUR_DIS_OTG BIT(8)
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#define MX53_BM_OVER_CUR_DIS_UHx BIT(30)
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#define MX53_USB_PHYCTRL1_PLLDIV_MASK 0x3
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#define MX53_USB_PLL_DIV_24_MHZ 0x01
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#define MX6_BM_OVER_CUR_DIS BIT(7)
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struct usbmisc_ops {
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/* It's called once when probe a usb device */
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int (*init)(struct imx_usbmisc_data *data);
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/* It's called once after adding a usb device */
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int (*post)(struct imx_usbmisc_data *data);
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};
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struct imx_usbmisc {
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void __iomem *base;
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spinlock_t lock;
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struct clk *clk;
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const struct usbmisc_ops *ops;
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};
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static struct imx_usbmisc *usbmisc;
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static int usbmisc_imx25_init(struct imx_usbmisc_data *data)
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{
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unsigned long flags;
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u32 val = 0;
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if (data->index > 1)
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return -EINVAL;
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spin_lock_irqsave(&usbmisc->lock, flags);
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switch (data->index) {
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case 0:
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val = readl(usbmisc->base);
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val &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PP_BIT);
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val |= (MX25_EHCI_INTERFACE_DIFF_UNI & MX25_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
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val |= (MX25_OTG_PM_BIT | MX25_OTG_OCPOL_BIT);
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writel(val, usbmisc->base);
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break;
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case 1:
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val = readl(usbmisc->base);
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val &= ~(MX25_H1_SIC_MASK | MX25_H1_PP_BIT | MX25_H1_IPPUE_UP_BIT);
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val |= (MX25_EHCI_INTERFACE_SINGLE_UNI & MX25_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
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val |= (MX25_H1_PM_BIT | MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
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MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT);
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writel(val, usbmisc->base);
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break;
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}
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spin_unlock_irqrestore(&usbmisc->lock, flags);
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return 0;
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}
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static int usbmisc_imx25_post(struct imx_usbmisc_data *data)
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{
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void __iomem *reg;
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unsigned long flags;
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u32 val;
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if (data->index > 2)
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return -EINVAL;
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reg = usbmisc->base + MX25_USB_PHY_CTRL_OFFSET;
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if (data->evdo) {
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spin_lock_irqsave(&usbmisc->lock, flags);
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val = readl(reg);
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writel(val | MX25_BM_EXTERNAL_VBUS_DIVIDER, reg);
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spin_unlock_irqrestore(&usbmisc->lock, flags);
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usleep_range(5000, 10000); /* needed to stabilize voltage */
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}
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return 0;
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}
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static int usbmisc_imx27_init(struct imx_usbmisc_data *data)
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{
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unsigned long flags;
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u32 val;
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switch (data->index) {
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case 0:
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val = MX27_OTG_PM_BIT;
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break;
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case 1:
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val = MX27_H1_PM_BIT;
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break;
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case 2:
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val = MX27_H2_PM_BIT;
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break;
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default:
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return -EINVAL;
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};
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spin_lock_irqsave(&usbmisc->lock, flags);
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if (data->disable_oc)
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val = readl(usbmisc->base) | val;
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else
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val = readl(usbmisc->base) & ~val;
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writel(val, usbmisc->base);
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spin_unlock_irqrestore(&usbmisc->lock, flags);
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return 0;
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}
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static int usbmisc_imx53_init(struct imx_usbmisc_data *data)
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{
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void __iomem *reg = NULL;
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unsigned long flags;
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u32 val = 0;
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if (data->index > 3)
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return -EINVAL;
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/* Select a 24 MHz reference clock for the PHY */
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reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET;
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val = readl(reg);
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val &= ~MX53_USB_PHYCTRL1_PLLDIV_MASK;
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val |= MX53_USB_PLL_DIV_24_MHZ;
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writel(val, usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET);
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if (data->disable_oc) {
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spin_lock_irqsave(&usbmisc->lock, flags);
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switch (data->index) {
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case 0:
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reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_0_OFFSET;
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val = readl(reg) | MX53_BM_OVER_CUR_DIS_OTG;
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break;
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case 1:
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reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_0_OFFSET;
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val = readl(reg) | MX53_BM_OVER_CUR_DIS_H1;
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break;
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case 2:
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reg = usbmisc->base + MX53_USB_UH2_CTRL_OFFSET;
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val = readl(reg) | MX53_BM_OVER_CUR_DIS_UHx;
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break;
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case 3:
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reg = usbmisc->base + MX53_USB_UH3_CTRL_OFFSET;
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val = readl(reg) | MX53_BM_OVER_CUR_DIS_UHx;
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break;
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}
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if (reg && val)
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writel(val, reg);
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spin_unlock_irqrestore(&usbmisc->lock, flags);
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}
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return 0;
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}
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static int usbmisc_imx6q_init(struct imx_usbmisc_data *data)
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{
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unsigned long flags;
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u32 reg;
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if (data->index > 3)
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return -EINVAL;
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if (data->disable_oc) {
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spin_lock_irqsave(&usbmisc->lock, flags);
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reg = readl(usbmisc->base + data->index * 4);
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writel(reg | MX6_BM_OVER_CUR_DIS,
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usbmisc->base + data->index * 4);
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spin_unlock_irqrestore(&usbmisc->lock, flags);
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}
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return 0;
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}
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static const struct usbmisc_ops imx25_usbmisc_ops = {
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.init = usbmisc_imx25_init,
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.post = usbmisc_imx25_post,
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};
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static const struct usbmisc_ops imx27_usbmisc_ops = {
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.init = usbmisc_imx27_init,
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};
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static const struct usbmisc_ops imx53_usbmisc_ops = {
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.init = usbmisc_imx53_init,
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};
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static const struct usbmisc_ops imx6q_usbmisc_ops = {
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.init = usbmisc_imx6q_init,
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};
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int imx_usbmisc_init(struct imx_usbmisc_data *data)
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{
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if (!usbmisc)
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return -EPROBE_DEFER;
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if (!usbmisc->ops->init)
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return 0;
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return usbmisc->ops->init(data);
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}
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EXPORT_SYMBOL_GPL(imx_usbmisc_init);
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int imx_usbmisc_init_post(struct imx_usbmisc_data *data)
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{
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if (!usbmisc)
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return -EPROBE_DEFER;
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if (!usbmisc->ops->post)
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return 0;
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return usbmisc->ops->post(data);
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}
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EXPORT_SYMBOL_GPL(imx_usbmisc_init_post);
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static const struct of_device_id usbmisc_imx_dt_ids[] = {
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{
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.compatible = "fsl,imx25-usbmisc",
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.data = &imx25_usbmisc_ops,
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},
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{
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.compatible = "fsl,imx35-usbmisc",
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.data = &imx25_usbmisc_ops,
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},
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{
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.compatible = "fsl,imx27-usbmisc",
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.data = &imx27_usbmisc_ops,
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},
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{
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.compatible = "fsl,imx51-usbmisc",
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.data = &imx53_usbmisc_ops,
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},
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{
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.compatible = "fsl,imx53-usbmisc",
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.data = &imx53_usbmisc_ops,
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},
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{
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.compatible = "fsl,imx6q-usbmisc",
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.data = &imx6q_usbmisc_ops,
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},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, usbmisc_imx_dt_ids);
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static int usbmisc_imx_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct imx_usbmisc *data;
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int ret;
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struct of_device_id *tmp_dev;
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if (usbmisc)
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return -EBUSY;
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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spin_lock_init(&data->lock);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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data->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(data->base))
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return PTR_ERR(data->base);
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data->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(data->clk)) {
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dev_err(&pdev->dev,
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"failed to get clock, err=%ld\n", PTR_ERR(data->clk));
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return PTR_ERR(data->clk);
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}
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ret = clk_prepare_enable(data->clk);
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if (ret) {
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dev_err(&pdev->dev,
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"clk_prepare_enable failed, err=%d\n", ret);
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return ret;
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}
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tmp_dev = (struct of_device_id *)
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of_match_device(usbmisc_imx_dt_ids, &pdev->dev);
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data->ops = (const struct usbmisc_ops *)tmp_dev->data;
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usbmisc = data;
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return 0;
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}
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static int usbmisc_imx_remove(struct platform_device *pdev)
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{
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clk_disable_unprepare(usbmisc->clk);
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usbmisc = NULL;
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return 0;
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}
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static struct platform_driver usbmisc_imx_driver = {
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.probe = usbmisc_imx_probe,
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.remove = usbmisc_imx_remove,
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.driver = {
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.name = "usbmisc_imx",
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.owner = THIS_MODULE,
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.of_match_table = usbmisc_imx_dt_ids,
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},
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};
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module_platform_driver(usbmisc_imx_driver);
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MODULE_ALIAS("platform:usbmisc-imx");
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("driver for imx usb non-core registers");
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MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>");
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