mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 21:16:54 +07:00
2275d7b575
Introduce two options to control the use of the tlbie instruction. A boot time option which completely disables the kernel using the instruction, this is currently incompatible with HASH MMU, KVM, and coherent accelerators. And a debugfs option can be switched at runtime and avoids using tlbie for invalidating CPU TLBs for normal process and kernel address mappings. Coherent accelerators are still managed with tlbie, as will KVM partition scope translations. Cross-CPU TLB flushing is implemented with IPIs and tlbiel. This is a basic implementation which does not attempt to make any optimisation beyond the tlbie implementation. This is useful for performance testing among other things. For example in certain situations on large systems, using IPIs may be faster than tlbie as they can be directed rather than broadcast. Later we may also take advantage of the IPIs to do more interesting things such as trim the mm cpumask more aggressively. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20190902152931.17840-7-npiggin@gmail.com
383 lines
8.7 KiB
C
383 lines
8.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2014 IBM Corp.
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*/
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#include <linux/spinlock.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/mutex.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/mm.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/idr.h>
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#include <linux/pci.h>
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#include <linux/sched/task.h>
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#include <asm/cputable.h>
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#include <asm/mmu.h>
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#include <misc/cxl-base.h>
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#include "cxl.h"
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#include "trace.h"
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static DEFINE_SPINLOCK(adapter_idr_lock);
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static DEFINE_IDR(cxl_adapter_idr);
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uint cxl_verbose;
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module_param_named(verbose, cxl_verbose, uint, 0600);
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MODULE_PARM_DESC(verbose, "Enable verbose dmesg output");
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const struct cxl_backend_ops *cxl_ops;
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int cxl_afu_slbia(struct cxl_afu *afu)
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{
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unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
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pr_devel("cxl_afu_slbia issuing SLBIA command\n");
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cxl_p2n_write(afu, CXL_SLBIA_An, CXL_TLB_SLB_IQ_ALL);
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while (cxl_p2n_read(afu, CXL_SLBIA_An) & CXL_TLB_SLB_P) {
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if (time_after_eq(jiffies, timeout)) {
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dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n");
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return -EBUSY;
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}
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/* If the adapter has gone down, we can assume that we
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* will PERST it and that will invalidate everything.
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*/
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if (!cxl_ops->link_ok(afu->adapter, afu))
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return -EIO;
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cpu_relax();
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}
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return 0;
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}
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static inline void _cxl_slbia(struct cxl_context *ctx, struct mm_struct *mm)
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{
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unsigned long flags;
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if (ctx->mm != mm)
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return;
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pr_devel("%s matched mm - card: %i afu: %i pe: %i\n", __func__,
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ctx->afu->adapter->adapter_num, ctx->afu->slice, ctx->pe);
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spin_lock_irqsave(&ctx->sste_lock, flags);
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trace_cxl_slbia(ctx);
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memset(ctx->sstp, 0, ctx->sst_size);
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spin_unlock_irqrestore(&ctx->sste_lock, flags);
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mb();
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cxl_afu_slbia(ctx->afu);
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}
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static inline void cxl_slbia_core(struct mm_struct *mm)
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{
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struct cxl *adapter;
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struct cxl_afu *afu;
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struct cxl_context *ctx;
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int card, slice, id;
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pr_devel("%s called\n", __func__);
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spin_lock(&adapter_idr_lock);
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idr_for_each_entry(&cxl_adapter_idr, adapter, card) {
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/* XXX: Make this lookup faster with link from mm to ctx */
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spin_lock(&adapter->afu_list_lock);
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for (slice = 0; slice < adapter->slices; slice++) {
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afu = adapter->afu[slice];
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if (!afu || !afu->enabled)
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continue;
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rcu_read_lock();
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idr_for_each_entry(&afu->contexts_idr, ctx, id)
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_cxl_slbia(ctx, mm);
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rcu_read_unlock();
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}
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spin_unlock(&adapter->afu_list_lock);
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}
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spin_unlock(&adapter_idr_lock);
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}
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static struct cxl_calls cxl_calls = {
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.cxl_slbia = cxl_slbia_core,
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.owner = THIS_MODULE,
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};
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int cxl_alloc_sst(struct cxl_context *ctx)
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{
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unsigned long vsid;
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u64 ea_mask, size, sstp0, sstp1;
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sstp0 = 0;
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sstp1 = 0;
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ctx->sst_size = PAGE_SIZE;
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ctx->sst_lru = 0;
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ctx->sstp = (struct cxl_sste *)get_zeroed_page(GFP_KERNEL);
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if (!ctx->sstp) {
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pr_err("cxl_alloc_sst: Unable to allocate segment table\n");
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return -ENOMEM;
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}
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pr_devel("SSTP allocated at 0x%p\n", ctx->sstp);
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vsid = get_kernel_vsid((u64)ctx->sstp, mmu_kernel_ssize) << 12;
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sstp0 |= (u64)mmu_kernel_ssize << CXL_SSTP0_An_B_SHIFT;
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sstp0 |= (SLB_VSID_KERNEL | mmu_psize_defs[mmu_linear_psize].sllp) << 50;
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size = (((u64)ctx->sst_size >> 8) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT;
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if (unlikely(size & ~CXL_SSTP0_An_SegTableSize_MASK)) {
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WARN(1, "Impossible segment table size\n");
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return -EINVAL;
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}
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sstp0 |= size;
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if (mmu_kernel_ssize == MMU_SEGSIZE_256M)
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ea_mask = 0xfffff00ULL;
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else
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ea_mask = 0xffffffff00ULL;
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sstp0 |= vsid >> (50-14); /* Top 14 bits of VSID */
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sstp1 |= (vsid << (64-(50-14))) & ~ea_mask;
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sstp1 |= (u64)ctx->sstp & ea_mask;
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sstp1 |= CXL_SSTP1_An_V;
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pr_devel("Looked up %#llx: slbfee. %#llx (ssize: %x, vsid: %#lx), copied to SSTP0: %#llx, SSTP1: %#llx\n",
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(u64)ctx->sstp, (u64)ctx->sstp & ESID_MASK, mmu_kernel_ssize, vsid, sstp0, sstp1);
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/* Store calculated sstp hardware points for use later */
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ctx->sstp0 = sstp0;
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ctx->sstp1 = sstp1;
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return 0;
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}
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/* print buffer content as integers when debugging */
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void cxl_dump_debug_buffer(void *buf, size_t buf_len)
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{
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#ifdef DEBUG
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int i, *ptr;
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/*
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* We want to regroup up to 4 integers per line, which means they
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* need to be in the same pr_devel() statement
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*/
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ptr = (int *) buf;
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for (i = 0; i * 4 < buf_len; i += 4) {
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if ((i + 3) * 4 < buf_len)
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pr_devel("%.8x %.8x %.8x %.8x\n", ptr[i], ptr[i + 1],
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ptr[i + 2], ptr[i + 3]);
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else if ((i + 2) * 4 < buf_len)
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pr_devel("%.8x %.8x %.8x\n", ptr[i], ptr[i + 1],
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ptr[i + 2]);
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else if ((i + 1) * 4 < buf_len)
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pr_devel("%.8x %.8x\n", ptr[i], ptr[i + 1]);
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else
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pr_devel("%.8x\n", ptr[i]);
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}
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#endif /* DEBUG */
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}
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/* Find a CXL adapter by it's number and increase it's refcount */
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struct cxl *get_cxl_adapter(int num)
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{
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struct cxl *adapter;
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spin_lock(&adapter_idr_lock);
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if ((adapter = idr_find(&cxl_adapter_idr, num)))
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get_device(&adapter->dev);
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spin_unlock(&adapter_idr_lock);
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return adapter;
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}
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static int cxl_alloc_adapter_nr(struct cxl *adapter)
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{
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int i;
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idr_preload(GFP_KERNEL);
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spin_lock(&adapter_idr_lock);
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i = idr_alloc(&cxl_adapter_idr, adapter, 0, 0, GFP_NOWAIT);
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spin_unlock(&adapter_idr_lock);
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idr_preload_end();
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if (i < 0)
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return i;
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adapter->adapter_num = i;
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return 0;
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}
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void cxl_remove_adapter_nr(struct cxl *adapter)
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{
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idr_remove(&cxl_adapter_idr, adapter->adapter_num);
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}
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struct cxl *cxl_alloc_adapter(void)
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{
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struct cxl *adapter;
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if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL)))
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return NULL;
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spin_lock_init(&adapter->afu_list_lock);
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if (cxl_alloc_adapter_nr(adapter))
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goto err1;
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if (dev_set_name(&adapter->dev, "card%i", adapter->adapter_num))
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goto err2;
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/* start with context lock taken */
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atomic_set(&adapter->contexts_num, -1);
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return adapter;
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err2:
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cxl_remove_adapter_nr(adapter);
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err1:
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kfree(adapter);
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return NULL;
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}
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struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice)
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{
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struct cxl_afu *afu;
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if (!(afu = kzalloc(sizeof(struct cxl_afu), GFP_KERNEL)))
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return NULL;
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afu->adapter = adapter;
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afu->dev.parent = &adapter->dev;
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afu->dev.release = cxl_ops->release_afu;
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afu->slice = slice;
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idr_init(&afu->contexts_idr);
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mutex_init(&afu->contexts_lock);
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spin_lock_init(&afu->afu_cntl_lock);
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atomic_set(&afu->configured_state, -1);
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afu->prefault_mode = CXL_PREFAULT_NONE;
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afu->irqs_max = afu->adapter->user_irqs;
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return afu;
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}
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int cxl_afu_select_best_mode(struct cxl_afu *afu)
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{
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if (afu->modes_supported & CXL_MODE_DIRECTED)
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return cxl_ops->afu_activate_mode(afu, CXL_MODE_DIRECTED);
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if (afu->modes_supported & CXL_MODE_DEDICATED)
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return cxl_ops->afu_activate_mode(afu, CXL_MODE_DEDICATED);
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dev_warn(&afu->dev, "No supported programming modes available\n");
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/* We don't fail this so the user can inspect sysfs */
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return 0;
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}
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int cxl_adapter_context_get(struct cxl *adapter)
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{
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int rc;
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rc = atomic_inc_unless_negative(&adapter->contexts_num);
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return rc ? 0 : -EBUSY;
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}
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void cxl_adapter_context_put(struct cxl *adapter)
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{
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atomic_dec_if_positive(&adapter->contexts_num);
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}
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int cxl_adapter_context_lock(struct cxl *adapter)
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{
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int rc;
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/* no active contexts -> contexts_num == 0 */
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rc = atomic_cmpxchg(&adapter->contexts_num, 0, -1);
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return rc ? -EBUSY : 0;
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}
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void cxl_adapter_context_unlock(struct cxl *adapter)
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{
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int val = atomic_cmpxchg(&adapter->contexts_num, -1, 0);
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/*
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* contexts lock taken -> contexts_num == -1
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* If not true then show a warning and force reset the lock.
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* This will happen when context_unlock was requested without
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* doing a context_lock.
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*/
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if (val != -1) {
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atomic_set(&adapter->contexts_num, 0);
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WARN(1, "Adapter context unlocked with %d active contexts",
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val);
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}
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}
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static int __init init_cxl(void)
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{
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int rc = 0;
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if (!tlbie_capable)
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return -EINVAL;
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if ((rc = cxl_file_init()))
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return rc;
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cxl_debugfs_init();
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/*
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* we don't register the callback on P9. slb callack is only
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* used for the PSL8 MMU and CX4.
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*/
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if (cxl_is_power8()) {
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rc = register_cxl_calls(&cxl_calls);
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if (rc)
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goto err;
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}
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if (cpu_has_feature(CPU_FTR_HVMODE)) {
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cxl_ops = &cxl_native_ops;
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rc = pci_register_driver(&cxl_pci_driver);
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}
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#ifdef CONFIG_PPC_PSERIES
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else {
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cxl_ops = &cxl_guest_ops;
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rc = platform_driver_register(&cxl_of_driver);
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}
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#endif
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if (rc)
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goto err1;
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return 0;
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err1:
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if (cxl_is_power8())
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unregister_cxl_calls(&cxl_calls);
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err:
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cxl_debugfs_exit();
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cxl_file_exit();
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return rc;
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}
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static void exit_cxl(void)
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{
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if (cpu_has_feature(CPU_FTR_HVMODE))
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pci_unregister_driver(&cxl_pci_driver);
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#ifdef CONFIG_PPC_PSERIES
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else
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platform_driver_unregister(&cxl_of_driver);
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#endif
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cxl_debugfs_exit();
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cxl_file_exit();
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if (cxl_is_power8())
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unregister_cxl_calls(&cxl_calls);
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idr_destroy(&cxl_adapter_idr);
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}
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module_init(init_cxl);
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module_exit(exit_cxl);
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MODULE_DESCRIPTION("IBM Coherent Accelerator");
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MODULE_AUTHOR("Ian Munsie <imunsie@au1.ibm.com>");
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MODULE_LICENSE("GPL");
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