mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 19:55:11 +07:00
1dc3485247
Be consistent with the rest of the code base. No functional change. v2: - fix sparse warnings for virtio_gpu_cmd_transfer_to_host_2d call. - move convert_to_hw_box helper function. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20191023062539.11728-2-kraxel@redhat.com
499 lines
12 KiB
C
499 lines
12 KiB
C
/*
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* Copyright (C) 2015 Red Hat, Inc.
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* All Rights Reserved.
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*
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* Authors:
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* Dave Airlie
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* Alon Levy
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/file.h>
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#include <linux/sync_file.h>
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#include <drm/drm_file.h>
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#include <drm/virtgpu_drm.h>
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#include "virtgpu_drv.h"
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static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct drm_virtgpu_map *virtio_gpu_map = data;
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return virtio_gpu_mode_dumb_mmap(file_priv, vgdev->ddev,
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virtio_gpu_map->handle,
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&virtio_gpu_map->offset);
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}
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/*
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* Usage of execbuffer:
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* Relocations need to take into account the full VIRTIO_GPUDrawable size.
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* However, the command as passed from user space must *not* contain the initial
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* VIRTIO_GPUReleaseInfo struct (first XXX bytes)
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*/
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static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
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struct drm_file *drm_file)
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{
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struct drm_virtgpu_execbuffer *exbuf = data;
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct virtio_gpu_fpriv *vfpriv = drm_file->driver_priv;
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struct virtio_gpu_fence *out_fence;
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int ret;
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uint32_t *bo_handles = NULL;
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void __user *user_bo_handles = NULL;
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struct virtio_gpu_object_array *buflist = NULL;
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struct sync_file *sync_file;
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int in_fence_fd = exbuf->fence_fd;
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int out_fence_fd = -1;
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void *buf;
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if (vgdev->has_virgl_3d == false)
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return -ENOSYS;
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if ((exbuf->flags & ~VIRTGPU_EXECBUF_FLAGS))
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return -EINVAL;
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exbuf->fence_fd = -1;
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if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_IN) {
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struct dma_fence *in_fence;
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in_fence = sync_file_get_fence(in_fence_fd);
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if (!in_fence)
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return -EINVAL;
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/*
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* Wait if the fence is from a foreign context, or if the fence
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* array contains any fence from a foreign context.
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*/
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ret = 0;
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if (!dma_fence_match_context(in_fence, vgdev->fence_drv.context))
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ret = dma_fence_wait(in_fence, true);
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dma_fence_put(in_fence);
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if (ret)
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return ret;
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}
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if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_OUT) {
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out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
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if (out_fence_fd < 0)
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return out_fence_fd;
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}
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if (exbuf->num_bo_handles) {
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bo_handles = kvmalloc_array(exbuf->num_bo_handles,
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sizeof(uint32_t), GFP_KERNEL);
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if (!bo_handles) {
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ret = -ENOMEM;
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goto out_unused_fd;
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}
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user_bo_handles = u64_to_user_ptr(exbuf->bo_handles);
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if (copy_from_user(bo_handles, user_bo_handles,
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exbuf->num_bo_handles * sizeof(uint32_t))) {
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ret = -EFAULT;
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goto out_unused_fd;
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}
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buflist = virtio_gpu_array_from_handles(drm_file, bo_handles,
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exbuf->num_bo_handles);
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if (!buflist) {
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ret = -ENOENT;
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goto out_unused_fd;
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}
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kvfree(bo_handles);
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bo_handles = NULL;
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}
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if (buflist) {
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ret = virtio_gpu_array_lock_resv(buflist);
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if (ret)
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goto out_unused_fd;
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}
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buf = vmemdup_user(u64_to_user_ptr(exbuf->command), exbuf->size);
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if (IS_ERR(buf)) {
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ret = PTR_ERR(buf);
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goto out_unresv;
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}
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out_fence = virtio_gpu_fence_alloc(vgdev);
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if(!out_fence) {
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ret = -ENOMEM;
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goto out_memdup;
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}
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if (out_fence_fd >= 0) {
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sync_file = sync_file_create(&out_fence->f);
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if (!sync_file) {
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dma_fence_put(&out_fence->f);
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ret = -ENOMEM;
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goto out_memdup;
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}
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exbuf->fence_fd = out_fence_fd;
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fd_install(out_fence_fd, sync_file->file);
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}
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virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
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vfpriv->ctx_id, buflist, out_fence);
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return 0;
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out_memdup:
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kvfree(buf);
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out_unresv:
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if (buflist)
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virtio_gpu_array_unlock_resv(buflist);
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out_unused_fd:
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kvfree(bo_handles);
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if (buflist)
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virtio_gpu_array_put_free(buflist);
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if (out_fence_fd >= 0)
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put_unused_fd(out_fence_fd);
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return ret;
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}
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static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct drm_virtgpu_getparam *param = data;
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int value;
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switch (param->param) {
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case VIRTGPU_PARAM_3D_FEATURES:
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value = vgdev->has_virgl_3d == true ? 1 : 0;
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break;
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case VIRTGPU_PARAM_CAPSET_QUERY_FIX:
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value = 1;
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break;
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default:
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return -EINVAL;
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}
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if (copy_to_user(u64_to_user_ptr(param->value), &value, sizeof(int)))
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return -EFAULT;
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return 0;
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}
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static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct drm_virtgpu_resource_create *rc = data;
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struct virtio_gpu_fence *fence;
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int ret;
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struct virtio_gpu_object *qobj;
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struct drm_gem_object *obj;
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uint32_t handle = 0;
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struct virtio_gpu_object_params params = { 0 };
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if (vgdev->has_virgl_3d == false) {
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if (rc->depth > 1)
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return -EINVAL;
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if (rc->nr_samples > 1)
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return -EINVAL;
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if (rc->last_level > 1)
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return -EINVAL;
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if (rc->target != 2)
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return -EINVAL;
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if (rc->array_size > 1)
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return -EINVAL;
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}
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params.format = rc->format;
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params.width = rc->width;
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params.height = rc->height;
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params.size = rc->size;
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if (vgdev->has_virgl_3d) {
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params.virgl = true;
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params.target = rc->target;
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params.bind = rc->bind;
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params.depth = rc->depth;
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params.array_size = rc->array_size;
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params.last_level = rc->last_level;
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params.nr_samples = rc->nr_samples;
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params.flags = rc->flags;
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}
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/* allocate a single page size object */
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if (params.size == 0)
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params.size = PAGE_SIZE;
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fence = virtio_gpu_fence_alloc(vgdev);
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if (!fence)
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return -ENOMEM;
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ret = virtio_gpu_object_create(vgdev, ¶ms, &qobj, fence);
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dma_fence_put(&fence->f);
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if (ret < 0)
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return ret;
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obj = &qobj->base.base;
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ret = drm_gem_handle_create(file_priv, obj, &handle);
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if (ret) {
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drm_gem_object_release(obj);
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return ret;
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}
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drm_gem_object_put_unlocked(obj);
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rc->res_handle = qobj->hw_res_handle; /* similiar to a VM address */
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rc->bo_handle = handle;
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return 0;
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}
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static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_virtgpu_resource_info *ri = data;
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struct drm_gem_object *gobj = NULL;
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struct virtio_gpu_object *qobj = NULL;
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gobj = drm_gem_object_lookup(file_priv, ri->bo_handle);
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if (gobj == NULL)
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return -ENOENT;
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qobj = gem_to_virtio_gpu_obj(gobj);
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ri->size = qobj->base.base.size;
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ri->res_handle = qobj->hw_res_handle;
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drm_gem_object_put_unlocked(gobj);
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return 0;
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}
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static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
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void *data,
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struct drm_file *file)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
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struct drm_virtgpu_3d_transfer_from_host *args = data;
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struct virtio_gpu_object_array *objs;
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struct virtio_gpu_fence *fence;
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int ret;
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u32 offset = args->offset;
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if (vgdev->has_virgl_3d == false)
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return -ENOSYS;
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objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
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if (objs == NULL)
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return -ENOENT;
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ret = virtio_gpu_array_lock_resv(objs);
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if (ret != 0)
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goto err_put_free;
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fence = virtio_gpu_fence_alloc(vgdev);
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if (!fence) {
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ret = -ENOMEM;
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goto err_unlock;
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}
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virtio_gpu_cmd_transfer_from_host_3d
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(vgdev, vfpriv->ctx_id, offset, args->level,
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&args->box, objs, fence);
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dma_fence_put(&fence->f);
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return 0;
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err_unlock:
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virtio_gpu_array_unlock_resv(objs);
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err_put_free:
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virtio_gpu_array_put_free(objs);
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return ret;
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}
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static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
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struct drm_virtgpu_3d_transfer_to_host *args = data;
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struct virtio_gpu_object_array *objs;
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struct virtio_gpu_fence *fence;
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int ret;
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u32 offset = args->offset;
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objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
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if (objs == NULL)
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return -ENOENT;
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if (!vgdev->has_virgl_3d) {
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virtio_gpu_cmd_transfer_to_host_2d
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(vgdev, offset,
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args->box.w, args->box.h, args->box.x, args->box.y,
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objs, NULL);
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} else {
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ret = virtio_gpu_array_lock_resv(objs);
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if (ret != 0)
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goto err_put_free;
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ret = -ENOMEM;
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fence = virtio_gpu_fence_alloc(vgdev);
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if (!fence)
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goto err_unlock;
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virtio_gpu_cmd_transfer_to_host_3d
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(vgdev,
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vfpriv ? vfpriv->ctx_id : 0, offset,
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args->level, &args->box, objs, fence);
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dma_fence_put(&fence->f);
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}
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return 0;
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err_unlock:
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virtio_gpu_array_unlock_resv(objs);
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err_put_free:
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virtio_gpu_array_put_free(objs);
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return ret;
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}
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static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct drm_virtgpu_3d_wait *args = data;
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struct drm_gem_object *obj;
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long timeout = 15 * HZ;
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int ret;
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obj = drm_gem_object_lookup(file, args->handle);
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if (obj == NULL)
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return -ENOENT;
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if (args->flags & VIRTGPU_WAIT_NOWAIT) {
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ret = dma_resv_test_signaled_rcu(obj->resv, true);
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} else {
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ret = dma_resv_wait_timeout_rcu(obj->resv, true, true,
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timeout);
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}
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if (ret == 0)
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ret = -EBUSY;
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else if (ret > 0)
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ret = 0;
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drm_gem_object_put_unlocked(obj);
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return ret;
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}
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static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
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void *data, struct drm_file *file)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct drm_virtgpu_get_caps *args = data;
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unsigned size, host_caps_size;
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int i;
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int found_valid = -1;
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int ret;
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struct virtio_gpu_drv_cap_cache *cache_ent;
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void *ptr;
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if (vgdev->num_capsets == 0)
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return -ENOSYS;
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/* don't allow userspace to pass 0 */
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if (args->size == 0)
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return -EINVAL;
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spin_lock(&vgdev->display_info_lock);
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for (i = 0; i < vgdev->num_capsets; i++) {
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if (vgdev->capsets[i].id == args->cap_set_id) {
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if (vgdev->capsets[i].max_version >= args->cap_set_ver) {
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found_valid = i;
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break;
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}
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}
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}
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if (found_valid == -1) {
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spin_unlock(&vgdev->display_info_lock);
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return -EINVAL;
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}
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host_caps_size = vgdev->capsets[found_valid].max_size;
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/* only copy to user the minimum of the host caps size or the guest caps size */
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size = min(args->size, host_caps_size);
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list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
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if (cache_ent->id == args->cap_set_id &&
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cache_ent->version == args->cap_set_ver) {
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spin_unlock(&vgdev->display_info_lock);
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goto copy_exit;
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}
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}
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spin_unlock(&vgdev->display_info_lock);
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/* not in cache - need to talk to hw */
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virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
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&cache_ent);
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copy_exit:
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ret = wait_event_timeout(vgdev->resp_wq,
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atomic_read(&cache_ent->is_valid), 5 * HZ);
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if (!ret)
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return -EBUSY;
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/* is_valid check must proceed before copy of the cache entry. */
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smp_rmb();
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ptr = cache_ent->caps_cache;
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if (copy_to_user(u64_to_user_ptr(args->addr), ptr, size))
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return -EFAULT;
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return 0;
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}
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struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
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DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
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DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
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DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
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DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
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virtio_gpu_resource_create_ioctl,
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DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
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DRM_RENDER_ALLOW),
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/* make transfer async to the main ring? - no sure, can we
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* thread these in the underlying GL
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*/
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DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
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virtio_gpu_transfer_from_host_ioctl,
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DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
|
|
virtio_gpu_transfer_to_host_ioctl,
|
|
DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
|
|
DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,
|
|
DRM_RENDER_ALLOW),
|
|
};
|