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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-02-15 17:37:23 +07:00
3dfd44c5f1
As the T4240 is based on corenet chassis v2.0 spec we update the global utilities (GUTS) device config compatiable to reflect this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
439 lines
11 KiB
Plaintext
439 lines
11 KiB
Plaintext
/*
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* T4240 Silicon/SoC Device Tree Source (post include)
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*
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* Copyright 2012 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,ifc", "simple-bus";
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interrupts = <25 2 0 0>;
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};
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/* controller at 0x240000 */
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&pci0 {
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compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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bus-range = <0x0 0xff>;
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interrupts = <20 2 0 0>;
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pcie@0 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <20 2 0 0>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 40 1 0 0
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0000 0 0 2 &mpic 1 1 0 0
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0000 0 0 3 &mpic 2 1 0 0
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0000 0 0 4 &mpic 3 1 0 0
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>;
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};
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};
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/* controller at 0x250000 */
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&pci1 {
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compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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bus-range = <0 0xff>;
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interrupts = <21 2 0 0>;
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pcie@0 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <21 2 0 0>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 41 1 0 0
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0000 0 0 2 &mpic 5 1 0 0
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0000 0 0 3 &mpic 6 1 0 0
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0000 0 0 4 &mpic 7 1 0 0
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>;
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};
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};
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/* controller at 0x260000 */
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&pci2 {
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compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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bus-range = <0x0 0xff>;
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interrupts = <22 2 0 0>;
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pcie@0 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <22 2 0 0>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 42 1 0 0
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0000 0 0 2 &mpic 9 1 0 0
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0000 0 0 3 &mpic 10 1 0 0
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0000 0 0 4 &mpic 11 1 0 0
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>;
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};
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};
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/* controller at 0x270000 */
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&pci3 {
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compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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bus-range = <0x0 0xff>;
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interrupts = <23 2 0 0>;
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pcie@0 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <23 2 0 0>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 43 1 0 0
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0000 0 0 2 &mpic 0 1 0 0
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0000 0 0 3 &mpic 4 1 0 0
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0000 0 0 4 &mpic 8 1 0 0
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>;
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};
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};
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&rio {
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compatible = "fsl,srio";
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interrupts = <16 2 1 11>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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port1 {
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#address-cells = <2>;
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#size-cells = <2>;
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cell-index = <1>;
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};
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port2 {
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#address-cells = <2>;
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#size-cells = <2>;
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cell-index = <2>;
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};
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};
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&dcsr {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,dcsr", "simple-bus";
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dcsr-epu@0 {
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compatible = "fsl,t4240-dcsr-epu", "fsl,dcsr-epu";
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interrupts = <52 2 0 0
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84 2 0 0
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85 2 0 0
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94 2 0 0
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95 2 0 0>;
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reg = <0x0 0x1000>;
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};
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dcsr-npc {
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compatible = "fsl,t4240-dcsr-cnpc", "fsl,dcsr-cnpc";
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reg = <0x1000 0x1000 0x1002000 0x10000>;
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};
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dcsr-nxc@2000 {
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compatible = "fsl,dcsr-nxc";
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reg = <0x2000 0x1000>;
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};
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dcsr-corenet {
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compatible = "fsl,dcsr-corenet";
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reg = <0x8000 0x1000 0x1A000 0x1000>;
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};
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dcsr-dpaa@9000 {
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compatible = "fsl,t4240-dcsr-dpaa", "fsl,dcsr-dpaa";
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reg = <0x9000 0x1000>;
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};
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dcsr-ocn@11000 {
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compatible = "fsl,t4240-dcsr-ocn", "fsl,dcsr-ocn";
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reg = <0x11000 0x1000>;
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};
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dcsr-ddr@12000 {
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compatible = "fsl,dcsr-ddr";
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dev-handle = <&ddr1>;
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reg = <0x12000 0x1000>;
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};
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dcsr-ddr@13000 {
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compatible = "fsl,dcsr-ddr";
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dev-handle = <&ddr2>;
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reg = <0x13000 0x1000>;
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};
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dcsr-ddr@14000 {
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compatible = "fsl,dcsr-ddr";
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dev-handle = <&ddr3>;
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reg = <0x14000 0x1000>;
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};
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dcsr-nal@18000 {
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compatible = "fsl,t4240-dcsr-nal", "fsl,dcsr-nal";
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reg = <0x18000 0x1000>;
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};
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dcsr-rcpm@22000 {
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compatible = "fsl,t4240-dcsr-rcpm", "fsl,dcsr-rcpm";
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reg = <0x22000 0x1000>;
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};
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dcsr-snpc@30000 {
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compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
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reg = <0x30000 0x1000 0x1022000 0x10000>;
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};
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dcsr-snpc@31000 {
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compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
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reg = <0x31000 0x1000 0x1042000 0x10000>;
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};
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dcsr-snpc@32000 {
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compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
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reg = <0x32000 0x1000 0x1062000 0x10000>;
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};
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dcsr-cpu-sb-proxy@100000 {
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compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu0>;
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reg = <0x100000 0x1000 0x101000 0x1000>;
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};
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dcsr-cpu-sb-proxy@108000 {
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compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu1>;
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reg = <0x108000 0x1000 0x109000 0x1000>;
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};
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dcsr-cpu-sb-proxy@110000 {
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compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu2>;
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reg = <0x110000 0x1000 0x111000 0x1000>;
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};
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dcsr-cpu-sb-proxy@118000 {
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compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu3>;
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reg = <0x118000 0x1000 0x119000 0x1000>;
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};
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dcsr-cpu-sb-proxy@120000 {
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compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu4>;
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reg = <0x120000 0x1000 0x121000 0x1000>;
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};
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dcsr-cpu-sb-proxy@128000 {
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compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu5>;
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reg = <0x128000 0x1000 0x129000 0x1000>;
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};
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dcsr-cpu-sb-proxy@130000 {
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compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu6>;
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reg = <0x130000 0x1000 0x131000 0x1000>;
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};
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dcsr-cpu-sb-proxy@138000 {
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compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu7>;
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reg = <0x138000 0x1000 0x139000 0x1000>;
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};
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dcsr-cpu-sb-proxy@140000 {
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compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu8>;
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reg = <0x140000 0x1000 0x141000 0x1000>;
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};
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dcsr-cpu-sb-proxy@148000 {
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compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu9>;
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reg = <0x148000 0x1000 0x149000 0x1000>;
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};
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dcsr-cpu-sb-proxy@150000 {
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compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu10>;
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reg = <0x150000 0x1000 0x151000 0x1000>;
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};
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dcsr-cpu-sb-proxy@158000 {
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compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu11>;
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reg = <0x158000 0x1000 0x159000 0x1000>;
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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soc-sram-error {
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compatible = "fsl,soc-sram-error";
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interrupts = <16 2 1 29>;
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};
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corenet-law@0 {
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compatible = "fsl,corenet-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <32>;
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};
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ddr1: memory-controller@8000 {
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compatible = "fsl,qoriq-memory-controller-v4.7",
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"fsl,qoriq-memory-controller";
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reg = <0x8000 0x1000>;
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interrupts = <16 2 1 23>;
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};
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ddr2: memory-controller@9000 {
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compatible = "fsl,qoriq-memory-controller-v4.7",
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"fsl,qoriq-memory-controller";
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reg = <0x9000 0x1000>;
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interrupts = <16 2 1 22>;
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};
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ddr3: memory-controller@a000 {
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compatible = "fsl,qoriq-memory-controller-v4.7",
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"fsl,qoriq-memory-controller";
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reg = <0xa000 0x1000>;
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interrupts = <16 2 1 21>;
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};
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cpc: l3-cache-controller@10000 {
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compatible = "fsl,t4240-l3-cache-controller", "cache";
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reg = <0x10000 0x1000
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0x11000 0x1000
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0x12000 0x1000>;
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interrupts = <16 2 1 27
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16 2 1 26
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16 2 1 25>;
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};
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corenet-cf@18000 {
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compatible = "fsl,corenet-cf";
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reg = <0x18000 0x1000>;
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interrupts = <16 2 1 31>;
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fsl,ccf-num-csdids = <32>;
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fsl,ccf-num-snoopids = <32>;
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};
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iommu@20000 {
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compatible = "fsl,pamu-v1.0", "fsl,pamu";
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reg = <0x20000 0x6000>;
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interrupts = <
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24 2 0 0
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16 2 1 30>;
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};
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/include/ "qoriq-mpic.dtsi"
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guts: global-utilities@e0000 {
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compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
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reg = <0xe0000 0xe00>;
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fsl,has-rstcr;
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fsl,liodn-bits = <12>;
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};
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clockgen: global-utilities@e1000 {
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compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2";
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reg = <0xe1000 0x1000>;
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};
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rcpm: global-utilities@e2000 {
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compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2";
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reg = <0xe2000 0x1000>;
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};
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sfp: sfp@e8000 {
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compatible = "fsl,t4240-sfp";
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reg = <0xe8000 0x1000>;
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};
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serdes: serdes@ea000 {
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compatible = "fsl,t4240-serdes";
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reg = <0xea000 0x4000>;
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};
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/include/ "qoriq-dma-0.dtsi"
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/include/ "qoriq-dma-1.dtsi"
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/include/ "qoriq-espi-0.dtsi"
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spi@110000 {
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fsl,espi-num-chipselects = <4>;
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};
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/include/ "qoriq-esdhc-0.dtsi"
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sdhc@114000 {
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compatible = "fsl,t4240-esdhc", "fsl,esdhc";
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sdhci,auto-cmd12;
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};
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/include/ "qoriq-i2c-0.dtsi"
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/include/ "qoriq-i2c-1.dtsi"
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/include/ "qoriq-duart-0.dtsi"
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/include/ "qoriq-duart-1.dtsi"
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/include/ "qoriq-gpio-0.dtsi"
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/include/ "qoriq-gpio-1.dtsi"
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/include/ "qoriq-gpio-2.dtsi"
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/include/ "qoriq-gpio-3.dtsi"
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/include/ "qoriq-usb2-mph-0.dtsi"
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usb0: usb@210000 {
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compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph";
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phy_type = "utmi";
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port0;
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};
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/include/ "qoriq-usb2-dr-0.dtsi"
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usb1: usb@211000 {
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compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
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dr_mode = "host";
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phy_type = "utmi";
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};
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/include/ "qoriq-sata2-0.dtsi"
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/include/ "qoriq-sata2-1.dtsi"
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/include/ "qoriq-sec5.0-0.dtsi"
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L2_1: l2-cache-controller@c20000 {
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compatible = "fsl,t4240-l2-cache-controller";
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reg = <0xc20000 0x40000>;
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next-level-cache = <&cpc>;
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};
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L2_2: l2-cache-controller@c60000 {
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compatible = "fsl,t4240-l2-cache-controller";
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reg = <0xc60000 0x40000>;
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next-level-cache = <&cpc>;
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};
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L2_3: l2-cache-controller@ca0000 {
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compatible = "fsl,t4240-l2-cache-controller";
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reg = <0xca0000 0x40000>;
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next-level-cache = <&cpc>;
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};
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};
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