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35a84dec00
We always set the IMO and FMO bits in the HCR_EL2 when running the guest, regardless if we use the vgic or not. By moving these flags to HCR_GUEST_FLAGS we can avoid one of the extra save/restore operations of HCR_EL2 in the world switch code, and we can also soon get rid of the other one. This is safe, because even though the IMO and FMO bits control both taking the interrupts to EL2 and remapping ICC_*_EL1 to ICV_*_EL1 when executed at EL1, as long as we ensure that these bits are clear when running the EL1 host, we're OK, because we reset the HCR_EL2 to only have the HCR_RW bit set when returning to EL1 on non-VHE systems. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shih-Wei Li <shihwei@cs.columbia.edu> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
247 lines
8.2 KiB
C
247 lines
8.2 KiB
C
/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ARM64_KVM_ARM_H__
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#define __ARM64_KVM_ARM_H__
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#include <asm/esr.h>
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#include <asm/memory.h>
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#include <asm/types.h>
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/* Hyp Configuration Register (HCR) bits */
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#define HCR_TEA (UL(1) << 37)
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#define HCR_TERR (UL(1) << 36)
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#define HCR_TLOR (UL(1) << 35)
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#define HCR_E2H (UL(1) << 34)
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#define HCR_ID (UL(1) << 33)
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#define HCR_CD (UL(1) << 32)
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#define HCR_RW_SHIFT 31
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#define HCR_RW (UL(1) << HCR_RW_SHIFT)
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#define HCR_TRVM (UL(1) << 30)
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#define HCR_HCD (UL(1) << 29)
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#define HCR_TDZ (UL(1) << 28)
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#define HCR_TGE (UL(1) << 27)
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#define HCR_TVM (UL(1) << 26)
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#define HCR_TTLB (UL(1) << 25)
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#define HCR_TPU (UL(1) << 24)
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#define HCR_TPC (UL(1) << 23)
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#define HCR_TSW (UL(1) << 22)
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#define HCR_TAC (UL(1) << 21)
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#define HCR_TIDCP (UL(1) << 20)
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#define HCR_TSC (UL(1) << 19)
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#define HCR_TID3 (UL(1) << 18)
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#define HCR_TID2 (UL(1) << 17)
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#define HCR_TID1 (UL(1) << 16)
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#define HCR_TID0 (UL(1) << 15)
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#define HCR_TWE (UL(1) << 14)
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#define HCR_TWI (UL(1) << 13)
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#define HCR_DC (UL(1) << 12)
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#define HCR_BSU (3 << 10)
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#define HCR_BSU_IS (UL(1) << 10)
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#define HCR_FB (UL(1) << 9)
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#define HCR_VSE (UL(1) << 8)
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#define HCR_VI (UL(1) << 7)
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#define HCR_VF (UL(1) << 6)
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#define HCR_AMO (UL(1) << 5)
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#define HCR_IMO (UL(1) << 4)
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#define HCR_FMO (UL(1) << 3)
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#define HCR_PTW (UL(1) << 2)
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#define HCR_SWIO (UL(1) << 1)
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#define HCR_VM (UL(1) << 0)
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/*
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* The bits we set in HCR:
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* TLOR: Trap LORegion register accesses
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* RW: 64bit by default, can be overridden for 32bit VMs
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* TAC: Trap ACTLR
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* TSC: Trap SMC
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* TVM: Trap VM ops (until M+C set in SCTLR_EL1)
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* TSW: Trap cache operations by set/way
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* TWE: Trap WFE
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* TWI: Trap WFI
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* TIDCP: Trap L2CTLR/L2ECTLR
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* BSU_IS: Upgrade barriers to the inner shareable domain
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* FB: Force broadcast of all maintainance operations
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* AMO: Override CPSR.A and enable signaling with VA
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* IMO: Override CPSR.I and enable signaling with VI
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* FMO: Override CPSR.F and enable signaling with VF
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* SWIO: Turn set/way invalidates into set/way clean+invalidate
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*/
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#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
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HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
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HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
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HCR_FMO | HCR_IMO)
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#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
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#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
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/* TCR_EL2 Registers bits */
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#define TCR_EL2_RES1 ((1 << 31) | (1 << 23))
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#define TCR_EL2_TBI (1 << 20)
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#define TCR_EL2_PS_SHIFT 16
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#define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_TG0_MASK TCR_TG0_MASK
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#define TCR_EL2_SH0_MASK TCR_SH0_MASK
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#define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
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#define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
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#define TCR_EL2_T0SZ_MASK 0x3f
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#define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
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TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)
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/* VTCR_EL2 Registers bits */
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#define VTCR_EL2_RES1 (1 << 31)
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#define VTCR_EL2_HD (1 << 22)
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#define VTCR_EL2_HA (1 << 21)
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#define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK
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#define VTCR_EL2_TG0_MASK TCR_TG0_MASK
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#define VTCR_EL2_TG0_4K TCR_TG0_4K
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#define VTCR_EL2_TG0_16K TCR_TG0_16K
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#define VTCR_EL2_TG0_64K TCR_TG0_64K
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#define VTCR_EL2_SH0_MASK TCR_SH0_MASK
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#define VTCR_EL2_SH0_INNER TCR_SH0_INNER
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#define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
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#define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA
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#define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
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#define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA
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#define VTCR_EL2_SL0_SHIFT 6
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#define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT)
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#define VTCR_EL2_SL0_LVL1 (1 << VTCR_EL2_SL0_SHIFT)
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#define VTCR_EL2_T0SZ_MASK 0x3f
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#define VTCR_EL2_T0SZ_40B 24
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#define VTCR_EL2_VS_SHIFT 19
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#define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT)
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#define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT)
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/*
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* We configure the Stage-2 page tables to always restrict the IPA space to be
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* 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are
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* not known to exist and will break with this configuration.
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*
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* VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time
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* (see hyp-init.S).
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*
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* Note that when using 4K pages, we concatenate two first level page tables
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* together. With 16K pages, we concatenate 16 first level page tables.
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*
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* The magic numbers used for VTTBR_X in this patch can be found in Tables
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* D4-23 and D4-25 in ARM DDI 0487A.b.
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*/
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#define VTCR_EL2_T0SZ_IPA VTCR_EL2_T0SZ_40B
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#define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
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VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)
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#ifdef CONFIG_ARM64_64K_PAGES
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/*
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* Stage2 translation configuration:
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* 64kB pages (TG0 = 1)
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* 2 level page tables (SL = 1)
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*/
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#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SL0_LVL1)
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#define VTTBR_X_TGRAN_MAGIC 38
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#elif defined(CONFIG_ARM64_16K_PAGES)
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/*
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* Stage2 translation configuration:
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* 16kB pages (TG0 = 2)
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* 2 level page tables (SL = 1)
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*/
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#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_16K | VTCR_EL2_SL0_LVL1)
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#define VTTBR_X_TGRAN_MAGIC 42
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#else /* 4K */
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/*
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* Stage2 translation configuration:
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* 4kB pages (TG0 = 0)
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* 3 level page tables (SL = 1)
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*/
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#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SL0_LVL1)
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#define VTTBR_X_TGRAN_MAGIC 37
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#endif
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#define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS)
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#define VTTBR_X (VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA)
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#define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_X)
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#define VTTBR_VMID_SHIFT (UL(48))
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#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
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/* Hyp System Trap Register */
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#define HSTR_EL2_T(x) (1 << x)
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/* Hyp Coprocessor Trap Register Shifts */
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#define CPTR_EL2_TFP_SHIFT 10
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/* Hyp Coprocessor Trap Register */
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#define CPTR_EL2_TCPAC (1 << 31)
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#define CPTR_EL2_TTA (1 << 20)
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#define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT)
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#define CPTR_EL2_TZ (1 << 8)
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#define CPTR_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 */
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#define CPTR_EL2_DEFAULT CPTR_EL2_RES1
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/* Hyp Debug Configuration Register bits */
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#define MDCR_EL2_TPMS (1 << 14)
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#define MDCR_EL2_E2PB_MASK (UL(0x3))
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#define MDCR_EL2_E2PB_SHIFT (UL(12))
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#define MDCR_EL2_TDRA (1 << 11)
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#define MDCR_EL2_TDOSA (1 << 10)
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#define MDCR_EL2_TDA (1 << 9)
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#define MDCR_EL2_TDE (1 << 8)
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#define MDCR_EL2_HPME (1 << 7)
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#define MDCR_EL2_TPM (1 << 6)
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#define MDCR_EL2_TPMCR (1 << 5)
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#define MDCR_EL2_HPMN_MASK (0x1F)
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/* For compatibility with fault code shared with 32-bit */
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#define FSC_FAULT ESR_ELx_FSC_FAULT
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#define FSC_ACCESS ESR_ELx_FSC_ACCESS
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#define FSC_PERM ESR_ELx_FSC_PERM
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#define FSC_SEA ESR_ELx_FSC_EXTABT
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#define FSC_SEA_TTW0 (0x14)
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#define FSC_SEA_TTW1 (0x15)
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#define FSC_SEA_TTW2 (0x16)
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#define FSC_SEA_TTW3 (0x17)
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#define FSC_SECC (0x18)
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#define FSC_SECC_TTW0 (0x1c)
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#define FSC_SECC_TTW1 (0x1d)
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#define FSC_SECC_TTW2 (0x1e)
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#define FSC_SECC_TTW3 (0x1f)
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/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
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#define HPFAR_MASK (~UL(0xf))
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#define kvm_arm_exception_type \
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{0, "IRQ" }, \
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{1, "TRAP" }
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#define ECN(x) { ESR_ELx_EC_##x, #x }
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#define kvm_arm_exception_class \
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ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
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ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(CP14_64), ECN(SVC64), \
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ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(IMP_DEF), ECN(IABT_LOW), \
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ECN(IABT_CUR), ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
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ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
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ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
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ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
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ECN(BKPT32), ECN(VECTOR32), ECN(BRK64)
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#define CPACR_EL1_FPEN (3 << 20)
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#define CPACR_EL1_TTA (1 << 28)
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#define CPACR_EL1_DEFAULT (CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN)
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#endif /* __ARM64_KVM_ARM_H__ */
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