Antoine Tenart 3de68d331c pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs ... The Marvell Berlin boards have a group based pinmuxing mechanism. This adds the core driver support. We actually do not need any information about the pins here and only have the definition of the groups. Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set to mode 0: Group Modes Offset Base Offset LSB Bit Width GSM12 3 sm_base 0x40 0x10 0x2 Ball Group Mode 0 Mode 1 Mode 2 BK4 GSM12 UART0_RX IrDA0_RX GPIO9 BH6 GSM12 UART0_TX IrDA0_TX GPIO10 So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need to set (sm_base + 0x40 + 0x10) &= ff3fffff. As pin control registers are part of either chip control or system control registers, that deal with a bunch of other functions we rely on a regmap instead of exclusively remapping any resources. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>		2014-05-23 00:05:00 +02:00
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berlin.c	pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs	2014-05-23 00:05:00 +02:00
berlin.h	pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs	2014-05-23 00:05:00 +02:00
Kconfig	pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs	2014-05-23 00:05:00 +02:00
Makefile	pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs	2014-05-23 00:05:00 +02:00