mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
de70d0e9d4
The i.MX 7ULP family of processors features NXP's advanced implementation of the Arm Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics Processing Units (GPUs). This patch aims to add an initial support for imx7ulp. Note that we need configure power mode to Partial Stop mode 3 with system/bus clock enabled first as the default enabled STOP mode will gate off system/bus clock when execute WFI in MX7ULP SoC. And there's still no MXC_CPU_IMX7ULP IDs read from register as ULP has no anatop as before. So we encode one with 0xff in reverse order in case new ones will be in the future. Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
30 lines
705 B
C
30 lines
705 B
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
|
* Copyright 2017-2018 NXP
|
|
* Author: Dong Aisheng <aisheng.dong@nxp.com>
|
|
*/
|
|
|
|
#include <linux/io.h>
|
|
#include <linux/of.h>
|
|
#include <linux/of_address.h>
|
|
|
|
#define SMC_PMCTRL 0x10
|
|
#define BP_PMCTRL_PSTOPO 16
|
|
#define PSTOPO_PSTOP3 0x3
|
|
|
|
void __init imx7ulp_pm_init(void)
|
|
{
|
|
struct device_node *np;
|
|
void __iomem *smc1_base;
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
|
|
smc1_base = of_iomap(np, 0);
|
|
WARN_ON(!smc1_base);
|
|
|
|
/* Partial Stop mode 3 with system/bus clock enabled */
|
|
writel_relaxed(PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO,
|
|
smc1_base + SMC_PMCTRL);
|
|
iounmap(smc1_base);
|
|
}
|