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3dca04d694
linux_dsm_epyc7002/arch/riscv/include/asm
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Linus Torvalds 3dca04d694 RISC-V Patches for the 4.20 Merge Window, Part 2 v2 
This tag contains the follow-on patches I'd like to target for the 4.20
 merge window.  I'm being somewhat conservative here, as while there are
 a few patches on the mailing list that were posted early in the merge
 window I'd like to let those bake for another round -- this was a fairly
 big release as far as RISC-V is concerened, and we need to walk before
 we can run.
 
 As far as the patches that made it go:
 
 * A patch to ignore offline CPUs when calculating AT_HWCAP.  This should
   fix GDB on the HiFive unleashed, which has an embedded core for hart
   0 which is exposed to Linux as an offline CPU.
 * A move of EM_RISCV to elf-em.h, which is where it should have been to
   begin with.
 * I've also removed the 64-bit divide routines.  I know I'm not really
   playing by my own rules here because I posted the patches this
   morning, but since they shouldn't be in the kernel I think it's better
   to err on the side of going too fast here.
 
 I don't anticipate any more patch sets for the merge window.
 
 Changes since v1:
 
 * Use a consistent base to merge from so the history isn't a mess.
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Merge tag 'riscv-for-linus-4.20-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux

Pull more RISC-V updates from Palmer Dabbelt:
 "This contains the follow-on patches I'd like to target for the 4.20
  merge window. I'm being somewhat conservative here, as while there are
  a few patches on the mailing list that were posted early in the merge
  window I'd like to let those bake for another round -- this was a
  fairly big release as far as RISC-V is concerened, and we need to walk
  before we can run.

  As far as the patches that made it go:

   - A patch to ignore offline CPUs when calculating AT_HWCAP. This
     should fix GDB on the HiFive unleashed, which has an embedded core
     for hart 0 which is exposed to Linux as an offline CPU.

   - A move of EM_RISCV to elf-em.h, which is where it should have been
     to begin with.

   - I've also removed the 64-bit divide routines. I know I'm not really
     playing by my own rules here because I posted the patches this
     morning, but since they shouldn't be in the kernel I think it's
     better to err on the side of going too fast here.

  I don't anticipate any more patch sets for the merge window"

* tag 'riscv-for-linus-4.20-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux:
  Move EM_RISCV into elf-em.h
  RISC-V: properly determine hardware caps
  Revert "lib: Add umoddi3 and udivmoddi4 of GCC library routines"
  Revert "RISC-V: Select GENERIC_LIB_UMODDI3 on RV32"
2018-10-31 16:20:28 -07:00
..
asm-offsets.h
asm-prototypes.h RISC-V: include linux/ftrace.h in asm-prototypes.h 2018-09-24 13:12:27 -07:00
asm.h RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros 2017-11-30 10:01:10 -08:00
atomic.h locking/atomics: Rework ordering barriers 2018-07-25 11:53:59 +02:00
barrier.h riscv/barrier: Define __smp_{store_release,load_acquire} 2018-04-02 19:59:43 -07:00
bitops.h RISC-V: __test_and_op_bit_ord should be strongly ordered 2017-11-28 14:04:05 -08:00
bug.h RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros 2017-11-30 10:01:10 -08:00
cache.h
cacheflush.h riscv: use NULL instead of a plain 0 2018-06-07 08:01:50 -07:00
cmpxchg.h riscv/atomic: Strengthen implementations with fences 2018-04-02 19:59:44 -07:00
csr.h RISC-V: add a definition for the SIE SEIE bit 2018-08-13 08:31:31 -07:00
current.h
delay.h
dma-mapping.h riscv: add swiotlb support 2018-05-19 08:46:26 +02:00
elf.h Move EM_RISCV into elf-em.h 2018-10-31 12:13:47 -07:00
fence.h riscv/spinlock: Strengthen implementations with fences 2018-04-02 19:59:43 -07:00
ftrace.h riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support 2018-04-02 19:59:13 -07:00
futex.h RISC-V: Add futex support. 2018-10-22 17:38:08 -07:00
hwcap.h
io.h riscv: remove CONFIG_MMU ifdefs 2018-01-07 15:14:39 -08:00
irq.h RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h 2018-08-13 08:31:31 -07:00
irqflags.h riscv: rename SR_* constants to match the spec 2018-01-07 15:14:39 -08:00
Kbuild RISC-V: Add futex support. 2018-10-22 17:38:08 -07:00
kprobes.h
linkage.h
mmu_context.h riscv: inline set_pgdir into its only caller 2018-01-30 19:16:17 -08:00
mmu.h RISC-V: Flush I$ when making a dirty page executable 2017-11-30 12:58:25 -08:00
module.h RISC-V: Add section of GOT.PLT for kernel module 2018-04-02 20:00:54 -07:00
page.h
pci.h PCI: remove PCI_DMA_BUS_IS_PHYS 2018-05-07 07:15:41 +02:00
perf_event.h RISC-V: Fix !CONFIG_SMP compilation error 2018-08-13 08:31:32 -07:00
pgalloc.h
pgtable-32.h
pgtable-64.h
pgtable-bits.h mm: introduce ARCH_HAS_PTE_SPECIAL 2018-06-07 17:34:35 -07:00
pgtable.h riscv: remove CONFIG_MMU ifdefs 2018-01-07 15:14:39 -08:00
processor.h treewide: remove current_text_addr 2018-10-31 08:54:12 -07:00
ptrace.h riscv: rename SR_* constants to match the spec 2018-01-07 15:14:39 -08:00
sbi.h
smp.h RISC-V: Show IPI stats 2018-10-22 17:03:37 -07:00
spinlock_types.h
spinlock.h riscv/spinlock: Strengthen implementations with fences 2018-04-02 19:59:43 -07:00
string.h
switch_to.h Auto-detect whether a FPU exists 2018-10-22 17:02:23 -07:00
syscall.h
thread_info.h Construct init thread stack in the linker script rather than by union 2018-01-09 23:21:02 +00:00
timex.h RISC-V: Use define for get_cycles like other architectures 2017-11-30 10:12:21 -08:00
tlb.h riscv: tlb: Provide definition of tlb_flush() before including tlb.h 2018-08-28 12:58:35 -07:00
tlbflush.h RISC-V: Use Linux logical CPU number instead of hartid 2018-10-22 17:03:37 -07:00
uaccess.h riscv: split the declaration of __copy_user 2018-06-09 12:34:31 -07:00
unistd.h RISC-V: Request newstat syscalls 2018-09-05 22:44:21 +02:00
vdso.h RISC-V: Define sys_riscv_flush_icache when SMP=n 2018-08-20 10:55:24 -07:00
word-at-a-time.h