mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
b1a3bfc97c
This driver was entered into staging a few cycles ago because there was not time to integrate the Realtek version into the support routines in the kernel. Now that there is an effort to converg the code base from Linux and the Realtek repo, it is time to move this driver. In addition, all the updates included in the 06/28/2014 version of the Realtek drivers are included here. With this change, it will be necessary to delete the staging driver. That will be handled in a separate patch. As it impacts the staging tree, such a patch is sent to a different destination. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
113 lines
3.1 KiB
C
113 lines
3.1 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2009-2014 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "pwrseq.h"
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/* drivers should parse below arrays and do the corresponding actions */
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/*3 Power on Array*/
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struct wlan_pwr_cfg rtl8192E_power_on_flow
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[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS +
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RTL8192E_TRANS_END_STEPS] = {
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RTL8192E_TRANS_CARDEMU_TO_ACT
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RTL8192E_TRANS_END
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};
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/*3Radio off GPIO Array */
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struct wlan_pwr_cfg rtl8192E_radio_off_flow
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[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS
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+ RTL8192E_TRANS_END_STEPS] = {
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RTL8192E_TRANS_ACT_TO_CARDEMU
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RTL8192E_TRANS_END
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};
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/*3Card Disable Array*/
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struct wlan_pwr_cfg rtl8192E_card_disable_flow
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[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
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RTL8192E_TRANS_END_STEPS] = {
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RTL8192E_TRANS_ACT_TO_CARDEMU
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RTL8192E_TRANS_CARDEMU_TO_CARDDIS
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RTL8192E_TRANS_END
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};
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/*3 Card Enable Array*/
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struct wlan_pwr_cfg rtl8192E_card_enable_flow
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[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
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RTL8192E_TRANS_END_STEPS] = {
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RTL8192E_TRANS_CARDDIS_TO_CARDEMU
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RTL8192E_TRANS_CARDEMU_TO_ACT
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RTL8192E_TRANS_END
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};
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/*3Suspend Array*/
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struct wlan_pwr_cfg rtl8192E_suspend_flow
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[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
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RTL8192E_TRANS_END_STEPS] = {
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RTL8192E_TRANS_ACT_TO_CARDEMU
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RTL8192E_TRANS_CARDEMU_TO_SUS
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RTL8192E_TRANS_END
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};
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/*3 Resume Array*/
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struct wlan_pwr_cfg rtl8192E_resume_flow
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[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS +
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RTL8192E_TRANS_END_STEPS] = {
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RTL8192E_TRANS_SUS_TO_CARDEMU
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RTL8192E_TRANS_CARDEMU_TO_ACT
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RTL8192E_TRANS_END
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};
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/*3HWPDN Array*/
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struct wlan_pwr_cfg rtl8192E_hwpdn_flow
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[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS +
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RTL8192E_TRANS_END_STEPS] = {
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RTL8192E_TRANS_ACT_TO_CARDEMU
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RTL8192E_TRANS_CARDEMU_TO_PDN
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RTL8192E_TRANS_END
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};
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/*3 Enter LPS */
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struct wlan_pwr_cfg rtl8192E_enter_lps_flow
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[RTL8192E_TRANS_ACT_TO_LPS_STEPS +
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RTL8192E_TRANS_END_STEPS] = {
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/*FW behavior*/
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RTL8192E_TRANS_ACT_TO_LPS
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RTL8192E_TRANS_END
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};
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/*3 Leave LPS */
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struct wlan_pwr_cfg rtl8192E_leave_lps_flow
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[RTL8192E_TRANS_LPS_TO_ACT_STEPS +
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RTL8192E_TRANS_END_STEPS] = {
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/*FW behavior*/
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RTL8192E_TRANS_LPS_TO_ACT
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RTL8192E_TRANS_END
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};
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