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ecd8081f6f
Install the callbacks via the state machine. Signed-off-by: Anna-Maria Gleixner <anna-maria@linutronix.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: linux-snps-arc@lists.infradead.org Cc: rt@linutronix.de Link: http://lkml.kernel.org/r/20160713153338.391826254@linutronix.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
380 lines
8.8 KiB
C
380 lines
8.8 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* vineetg: Jan 1011
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* -sched_clock( ) no longer jiffies based. Uses the same clocksource
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* as gtod
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*
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* Rajeshwarr/Vineetg: Mar 2008
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* -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code)
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* for arch independent gettimeofday()
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* -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers
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*
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* Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c
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*/
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/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1
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* Each can programmed to go from @count to @limit and optionally
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* interrupt when that happens.
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* A write to Control Register clears the Interrupt
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*
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* We've designated TIMER0 for events (clockevents)
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* while TIMER1 for free running (clocksource)
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*
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* Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1
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* which however is currently broken
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*/
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/cpu.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <asm/irq.h>
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#include <asm/arcregs.h>
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#include <asm/mcip.h>
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/* Timer related Aux registers */
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#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
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#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
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#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
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#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
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#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
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#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
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#define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
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#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
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#define ARC_TIMER_MAX 0xFFFFFFFF
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static unsigned long arc_timer_freq;
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static int noinline arc_get_timer_clk(struct device_node *node)
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{
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struct clk *clk;
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int ret;
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("timer missing clk");
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return PTR_ERR(clk);
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("Couldn't enable parent clk\n");
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return ret;
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}
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arc_timer_freq = clk_get_rate(clk);
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return 0;
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}
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/********** Clock Source Device *********/
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#ifdef CONFIG_ARC_HAS_GFRC
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static cycle_t arc_read_gfrc(struct clocksource *cs)
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{
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unsigned long flags;
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union {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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struct { u32 h, l; };
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#else
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struct { u32 l, h; };
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#endif
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cycle_t full;
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} stamp;
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local_irq_save(flags);
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__mcip_cmd(CMD_GFRC_READ_LO, 0);
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stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK);
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__mcip_cmd(CMD_GFRC_READ_HI, 0);
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stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK);
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local_irq_restore(flags);
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return stamp.full;
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}
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static struct clocksource arc_counter_gfrc = {
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.name = "ARConnect GFRC",
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.rating = 400,
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.read = arc_read_gfrc,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init arc_cs_setup_gfrc(struct device_node *node)
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{
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int exists = cpuinfo_arc700[0].extn.gfrc;
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int ret;
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if (WARN(!exists, "Global-64-bit-Ctr clocksource not detected"))
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return -ENXIO;
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ret = arc_get_timer_clk(node);
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if (ret)
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return ret;
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return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
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}
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CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
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#endif
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#ifdef CONFIG_ARC_HAS_RTC
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#define AUX_RTC_CTRL 0x103
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#define AUX_RTC_LOW 0x104
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#define AUX_RTC_HIGH 0x105
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static cycle_t arc_read_rtc(struct clocksource *cs)
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{
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unsigned long status;
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union {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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struct { u32 high, low; };
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#else
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struct { u32 low, high; };
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#endif
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cycle_t full;
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} stamp;
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__asm__ __volatile(
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"1: \n"
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" lr %0, [AUX_RTC_LOW] \n"
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" lr %1, [AUX_RTC_HIGH] \n"
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" lr %2, [AUX_RTC_CTRL] \n"
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" bbit0.nt %2, 31, 1b \n"
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: "=r" (stamp.low), "=r" (stamp.high), "=r" (status));
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return stamp.full;
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}
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static struct clocksource arc_counter_rtc = {
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.name = "ARCv2 RTC",
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.rating = 350,
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.read = arc_read_rtc,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init arc_cs_setup_rtc(struct device_node *node)
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{
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int exists = cpuinfo_arc700[smp_processor_id()].extn.rtc;
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int ret;
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if (WARN(!exists, "Local-64-bit-Ctr clocksource not detected"))
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return -ENXIO;
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/* Local to CPU hence not usable in SMP */
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if (WARN(IS_ENABLED(CONFIG_SMP), "Local-64-bit-Ctr not usable in SMP"))
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return -EINVAL;
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ret = arc_get_timer_clk(node);
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if (ret)
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return ret;
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write_aux_reg(AUX_RTC_CTRL, 1);
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return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
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}
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CLOCKSOURCE_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
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#endif
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/*
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* 32bit TIMER1 to keep counting monotonically and wraparound
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*/
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static cycle_t arc_read_timer1(struct clocksource *cs)
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{
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return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
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}
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static struct clocksource arc_counter_timer1 = {
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.name = "ARC Timer1",
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.rating = 300,
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.read = arc_read_timer1,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init arc_cs_setup_timer1(struct device_node *node)
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{
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int ret;
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/* Local to CPU hence not usable in SMP */
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if (IS_ENABLED(CONFIG_SMP))
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return -EINVAL;
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ret = arc_get_timer_clk(node);
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if (ret)
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return ret;
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write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
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write_aux_reg(ARC_REG_TIMER1_CNT, 0);
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write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
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return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
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}
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/********** Clock Event Device *********/
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static int arc_timer_irq;
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/*
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* Arm the timer to interrupt after @cycles
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* The distinction for oneshot/periodic is done in arc_event_timer_ack() below
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*/
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static void arc_timer_event_setup(unsigned int cycles)
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{
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write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
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write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
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write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
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}
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static int arc_clkevent_set_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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arc_timer_event_setup(delta);
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return 0;
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}
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static int arc_clkevent_set_periodic(struct clock_event_device *dev)
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{
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/*
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* At X Hz, 1 sec = 1000ms -> X cycles;
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* 10ms -> X / 100 cycles
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*/
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arc_timer_event_setup(arc_timer_freq / HZ);
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return 0;
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}
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static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
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.name = "ARC Timer0",
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.features = CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_PERIODIC,
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.rating = 300,
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.set_next_event = arc_clkevent_set_next_event,
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.set_state_periodic = arc_clkevent_set_periodic,
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};
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static irqreturn_t timer_irq_handler(int irq, void *dev_id)
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{
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/*
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* Note that generic IRQ core could have passed @evt for @dev_id if
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* irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
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*/
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struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
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int irq_reenable = clockevent_state_periodic(evt);
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/*
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* Any write to CTRL reg ACks the interrupt, we rewrite the
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* Count when [N]ot [H]alted bit.
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* And re-arm it if perioid by [I]nterrupt [E]nable bit
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*/
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write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static int arc_timer_starting_cpu(unsigned int cpu)
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{
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struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
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evt->cpumask = cpumask_of(smp_processor_id());
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clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMER_MAX);
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enable_percpu_irq(arc_timer_irq, 0);
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return 0;
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}
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static int arc_timer_dying_cpu(unsigned int cpu)
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{
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disable_percpu_irq(arc_timer_irq);
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return 0;
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}
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/*
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* clockevent setup for boot CPU
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*/
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static int __init arc_clockevent_setup(struct device_node *node)
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{
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struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
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int ret;
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arc_timer_irq = irq_of_parse_and_map(node, 0);
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if (arc_timer_irq <= 0) {
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pr_err("clockevent: missing irq");
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return -EINVAL;
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}
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ret = arc_get_timer_clk(node);
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if (ret) {
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pr_err("clockevent: missing clk");
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return ret;
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}
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/* Needs apriori irq_set_percpu_devid() done in intc map function */
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ret = request_percpu_irq(arc_timer_irq, timer_irq_handler,
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"Timer0 (per-cpu-tick)", evt);
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if (ret) {
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pr_err("clockevent: unable to request irq\n");
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return ret;
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}
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ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
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"AP_ARC_TIMER_STARTING",
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arc_timer_starting_cpu,
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arc_timer_dying_cpu);
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if (ret) {
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pr_err("Failed to setup hotplug state");
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return ret;
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}
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return 0;
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}
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static int __init arc_of_timer_init(struct device_node *np)
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{
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static int init_count = 0;
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int ret;
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if (!init_count) {
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init_count = 1;
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ret = arc_clockevent_setup(np);
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} else {
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ret = arc_cs_setup_timer1(np);
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}
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return ret;
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}
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CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);
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/*
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* Called from start_kernel() - boot CPU only
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*/
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void __init time_init(void)
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{
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of_clk_init(NULL);
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clocksource_probe();
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}
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