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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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3d9dd6fdd2
The EMC driver needs to know the number of external memory devices and also needs to update the EMEM configuration based on the new rate of the memory bus. To know how to update the EMEM config, looks up the values of the burst regs in the DT, for a given timing. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
1040 lines
17 KiB
C
1040 lines
17 KiB
C
/*
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* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/of.h>
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#include <linux/mm.h>
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#include <asm/cacheflush.h>
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#include <dt-bindings/memory/tegra124-mc.h>
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#include "mc.h"
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#define MC_EMEM_ARB_CFG 0x90
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#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
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#define MC_EMEM_ARB_TIMING_RCD 0x98
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#define MC_EMEM_ARB_TIMING_RP 0x9c
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#define MC_EMEM_ARB_TIMING_RC 0xa0
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#define MC_EMEM_ARB_TIMING_RAS 0xa4
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#define MC_EMEM_ARB_TIMING_FAW 0xa8
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#define MC_EMEM_ARB_TIMING_RRD 0xac
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#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
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#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
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#define MC_EMEM_ARB_TIMING_R2R 0xb8
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#define MC_EMEM_ARB_TIMING_W2W 0xbc
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#define MC_EMEM_ARB_TIMING_R2W 0xc0
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#define MC_EMEM_ARB_TIMING_W2R 0xc4
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#define MC_EMEM_ARB_DA_TURNS 0xd0
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#define MC_EMEM_ARB_DA_COVERS 0xd4
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#define MC_EMEM_ARB_MISC0 0xd8
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#define MC_EMEM_ARB_MISC1 0xdc
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#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
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static const unsigned long tegra124_mc_emem_regs[] = {
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MC_EMEM_ARB_CFG,
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MC_EMEM_ARB_OUTSTANDING_REQ,
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MC_EMEM_ARB_TIMING_RCD,
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MC_EMEM_ARB_TIMING_RP,
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MC_EMEM_ARB_TIMING_RC,
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MC_EMEM_ARB_TIMING_RAS,
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MC_EMEM_ARB_TIMING_FAW,
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MC_EMEM_ARB_TIMING_RRD,
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MC_EMEM_ARB_TIMING_RAP2PRE,
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MC_EMEM_ARB_TIMING_WAP2PRE,
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MC_EMEM_ARB_TIMING_R2R,
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MC_EMEM_ARB_TIMING_W2W,
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MC_EMEM_ARB_TIMING_R2W,
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MC_EMEM_ARB_TIMING_W2R,
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MC_EMEM_ARB_DA_TURNS,
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MC_EMEM_ARB_DA_COVERS,
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MC_EMEM_ARB_MISC0,
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MC_EMEM_ARB_MISC1,
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MC_EMEM_ARB_RING1_THROTTLE
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};
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static const struct tegra_mc_client tegra124_mc_clients[] = {
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{
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.id = 0x00,
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.name = "ptcr",
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.swgroup = TEGRA_SWGROUP_PTC,
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}, {
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.id = 0x01,
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.name = "display0a",
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.swgroup = TEGRA_SWGROUP_DC,
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.smmu = {
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.reg = 0x228,
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.bit = 1,
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},
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.la = {
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.reg = 0x2e8,
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.shift = 0,
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.mask = 0xff,
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.def = 0xc2,
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},
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}, {
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.id = 0x02,
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.name = "display0ab",
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.swgroup = TEGRA_SWGROUP_DCB,
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.smmu = {
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.reg = 0x228,
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.bit = 2,
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},
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.la = {
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.reg = 0x2f4,
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.shift = 0,
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.mask = 0xff,
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.def = 0xc6,
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},
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}, {
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.id = 0x03,
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.name = "display0b",
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.swgroup = TEGRA_SWGROUP_DC,
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.smmu = {
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.reg = 0x228,
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.bit = 3,
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},
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.la = {
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.reg = 0x2e8,
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.shift = 16,
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.mask = 0xff,
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.def = 0x50,
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},
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}, {
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.id = 0x04,
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.name = "display0bb",
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.swgroup = TEGRA_SWGROUP_DCB,
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.smmu = {
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.reg = 0x228,
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.bit = 4,
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},
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.la = {
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.reg = 0x2f4,
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.shift = 16,
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.mask = 0xff,
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.def = 0x50,
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},
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}, {
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.id = 0x05,
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.name = "display0c",
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.swgroup = TEGRA_SWGROUP_DC,
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.smmu = {
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.reg = 0x228,
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.bit = 5,
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},
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.la = {
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.reg = 0x2ec,
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.shift = 0,
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.mask = 0xff,
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.def = 0x50,
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},
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}, {
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.id = 0x06,
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.name = "display0cb",
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.swgroup = TEGRA_SWGROUP_DCB,
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.smmu = {
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.reg = 0x228,
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.bit = 6,
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},
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.la = {
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.reg = 0x2f8,
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.shift = 0,
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.mask = 0xff,
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.def = 0x50,
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},
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}, {
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.id = 0x0e,
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.name = "afir",
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.swgroup = TEGRA_SWGROUP_AFI,
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.smmu = {
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.reg = 0x228,
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.bit = 14,
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},
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.la = {
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.reg = 0x2e0,
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.shift = 0,
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.mask = 0xff,
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.def = 0x13,
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},
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}, {
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.id = 0x0f,
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.name = "avpcarm7r",
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.swgroup = TEGRA_SWGROUP_AVPC,
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.smmu = {
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.reg = 0x228,
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.bit = 15,
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},
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.la = {
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.reg = 0x2e4,
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.shift = 0,
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.mask = 0xff,
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.def = 0x04,
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},
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}, {
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.id = 0x10,
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.name = "displayhc",
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.swgroup = TEGRA_SWGROUP_DC,
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.smmu = {
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.reg = 0x228,
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.bit = 16,
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},
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.la = {
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.reg = 0x2f0,
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.shift = 0,
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.mask = 0xff,
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.def = 0x50,
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},
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}, {
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.id = 0x11,
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.name = "displayhcb",
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.swgroup = TEGRA_SWGROUP_DCB,
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.smmu = {
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.reg = 0x228,
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.bit = 17,
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},
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.la = {
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.reg = 0x2fc,
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.shift = 0,
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.mask = 0xff,
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.def = 0x50,
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},
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}, {
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.id = 0x15,
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.name = "hdar",
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.swgroup = TEGRA_SWGROUP_HDA,
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.smmu = {
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.reg = 0x228,
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.bit = 21,
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},
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.la = {
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.reg = 0x318,
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.shift = 0,
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.mask = 0xff,
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.def = 0x24,
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},
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}, {
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.id = 0x16,
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.name = "host1xdmar",
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.swgroup = TEGRA_SWGROUP_HC,
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.smmu = {
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.reg = 0x228,
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.bit = 22,
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},
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.la = {
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.reg = 0x310,
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.shift = 0,
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.mask = 0xff,
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.def = 0x1e,
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},
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}, {
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.id = 0x17,
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.name = "host1xr",
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.swgroup = TEGRA_SWGROUP_HC,
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.smmu = {
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.reg = 0x228,
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.bit = 23,
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},
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.la = {
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.reg = 0x310,
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.shift = 16,
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.mask = 0xff,
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.def = 0x50,
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},
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}, {
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.id = 0x1c,
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.name = "msencsrd",
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.swgroup = TEGRA_SWGROUP_MSENC,
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.smmu = {
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.reg = 0x228,
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.bit = 28,
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},
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.la = {
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.reg = 0x328,
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.shift = 0,
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.mask = 0xff,
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.def = 0x23,
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},
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}, {
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.id = 0x1d,
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.name = "ppcsahbdmar",
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.swgroup = TEGRA_SWGROUP_PPCS,
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.smmu = {
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.reg = 0x228,
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.bit = 29,
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},
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.la = {
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.reg = 0x344,
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.shift = 0,
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.mask = 0xff,
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.def = 0x49,
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},
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}, {
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.id = 0x1e,
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.name = "ppcsahbslvr",
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.swgroup = TEGRA_SWGROUP_PPCS,
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.smmu = {
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.reg = 0x228,
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.bit = 30,
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},
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.la = {
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.reg = 0x344,
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.shift = 16,
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.mask = 0xff,
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.def = 0x1a,
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},
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}, {
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.id = 0x1f,
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.name = "satar",
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.swgroup = TEGRA_SWGROUP_SATA,
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.smmu = {
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.reg = 0x228,
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.bit = 31,
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},
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.la = {
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.reg = 0x350,
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.shift = 0,
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.mask = 0xff,
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.def = 0x65,
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},
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}, {
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.id = 0x22,
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.name = "vdebsevr",
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.swgroup = TEGRA_SWGROUP_VDE,
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.smmu = {
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.reg = 0x22c,
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.bit = 2,
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},
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.la = {
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.reg = 0x354,
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.shift = 0,
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.mask = 0xff,
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.def = 0x4f,
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},
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}, {
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.id = 0x23,
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.name = "vdember",
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.swgroup = TEGRA_SWGROUP_VDE,
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.smmu = {
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.reg = 0x22c,
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.bit = 3,
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},
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.la = {
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.reg = 0x354,
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.shift = 16,
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.mask = 0xff,
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.def = 0x3d,
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},
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}, {
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.id = 0x24,
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.name = "vdemcer",
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.swgroup = TEGRA_SWGROUP_VDE,
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.smmu = {
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.reg = 0x22c,
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.bit = 4,
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},
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.la = {
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.reg = 0x358,
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.shift = 0,
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.mask = 0xff,
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.def = 0x66,
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},
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}, {
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.id = 0x25,
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.name = "vdetper",
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.swgroup = TEGRA_SWGROUP_VDE,
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.smmu = {
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.reg = 0x22c,
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.bit = 5,
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},
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.la = {
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.reg = 0x358,
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.shift = 16,
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.mask = 0xff,
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.def = 0xa5,
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},
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}, {
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.id = 0x26,
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.name = "mpcorelpr",
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.swgroup = TEGRA_SWGROUP_MPCORELP,
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.la = {
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.reg = 0x324,
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.shift = 0,
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.mask = 0xff,
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.def = 0x04,
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},
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}, {
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.id = 0x27,
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.name = "mpcorer",
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.swgroup = TEGRA_SWGROUP_MPCORE,
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.la = {
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.reg = 0x320,
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.shift = 0,
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.mask = 0xff,
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.def = 0x04,
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},
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}, {
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.id = 0x2b,
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.name = "msencswr",
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.swgroup = TEGRA_SWGROUP_MSENC,
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.smmu = {
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.reg = 0x22c,
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.bit = 11,
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},
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.la = {
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.reg = 0x328,
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.shift = 16,
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.mask = 0xff,
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.def = 0x80,
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},
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}, {
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.id = 0x31,
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.name = "afiw",
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.swgroup = TEGRA_SWGROUP_AFI,
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.smmu = {
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.reg = 0x22c,
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.bit = 17,
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},
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.la = {
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.reg = 0x2e0,
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.shift = 16,
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.mask = 0xff,
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.def = 0x80,
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},
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}, {
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.id = 0x32,
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.name = "avpcarm7w",
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.swgroup = TEGRA_SWGROUP_AVPC,
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.smmu = {
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.reg = 0x22c,
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.bit = 18,
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},
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.la = {
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.reg = 0x2e4,
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.shift = 16,
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.mask = 0xff,
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.def = 0x80,
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},
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}, {
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.id = 0x35,
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.name = "hdaw",
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.swgroup = TEGRA_SWGROUP_HDA,
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.smmu = {
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.reg = 0x22c,
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.bit = 21,
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},
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.la = {
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.reg = 0x318,
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.shift = 16,
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.mask = 0xff,
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.def = 0x80,
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},
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}, {
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.id = 0x36,
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.name = "host1xw",
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.swgroup = TEGRA_SWGROUP_HC,
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.smmu = {
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.reg = 0x22c,
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.bit = 22,
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},
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.la = {
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.reg = 0x314,
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.shift = 0,
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.mask = 0xff,
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.def = 0x80,
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},
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}, {
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.id = 0x38,
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.name = "mpcorelpw",
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.swgroup = TEGRA_SWGROUP_MPCORELP,
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.la = {
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.reg = 0x324,
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.shift = 16,
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.mask = 0xff,
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.def = 0x80,
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},
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}, {
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.id = 0x39,
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.name = "mpcorew",
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.swgroup = TEGRA_SWGROUP_MPCORE,
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.la = {
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.reg = 0x320,
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.shift = 16,
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.mask = 0xff,
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.def = 0x80,
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},
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}, {
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.id = 0x3b,
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.name = "ppcsahbdmaw",
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.swgroup = TEGRA_SWGROUP_PPCS,
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.smmu = {
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.reg = 0x22c,
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.bit = 27,
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},
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.la = {
|
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.reg = 0x348,
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.shift = 0,
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.mask = 0xff,
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.def = 0x80,
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},
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}, {
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.id = 0x3c,
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.name = "ppcsahbslvw",
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.swgroup = TEGRA_SWGROUP_PPCS,
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.smmu = {
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.reg = 0x22c,
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.bit = 28,
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},
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.la = {
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.reg = 0x348,
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.shift = 16,
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.mask = 0xff,
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.def = 0x80,
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},
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}, {
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.id = 0x3d,
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.name = "sataw",
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.swgroup = TEGRA_SWGROUP_SATA,
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.smmu = {
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.reg = 0x22c,
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.bit = 29,
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},
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.la = {
|
|
.reg = 0x350,
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.shift = 16,
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.mask = 0xff,
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.def = 0x65,
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},
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}, {
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.id = 0x3e,
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.name = "vdebsevw",
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|
.swgroup = TEGRA_SWGROUP_VDE,
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.smmu = {
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.reg = 0x22c,
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.bit = 30,
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},
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.la = {
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.reg = 0x35c,
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.shift = 0,
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.mask = 0xff,
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.def = 0x80,
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},
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}, {
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.id = 0x3f,
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.name = "vdedbgw",
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.swgroup = TEGRA_SWGROUP_VDE,
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.smmu = {
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.reg = 0x22c,
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.bit = 31,
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},
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.la = {
|
|
.reg = 0x35c,
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|
.shift = 16,
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.mask = 0xff,
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.def = 0x80,
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},
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}, {
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.id = 0x40,
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|
.name = "vdembew",
|
|
.swgroup = TEGRA_SWGROUP_VDE,
|
|
.smmu = {
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.reg = 0x230,
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.bit = 0,
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},
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.la = {
|
|
.reg = 0x360,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x41,
|
|
.name = "vdetpmw",
|
|
.swgroup = TEGRA_SWGROUP_VDE,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 1,
|
|
},
|
|
.la = {
|
|
.reg = 0x360,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x44,
|
|
.name = "ispra",
|
|
.swgroup = TEGRA_SWGROUP_ISP2,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 4,
|
|
},
|
|
.la = {
|
|
.reg = 0x370,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x18,
|
|
},
|
|
}, {
|
|
.id = 0x46,
|
|
.name = "ispwa",
|
|
.swgroup = TEGRA_SWGROUP_ISP2,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 6,
|
|
},
|
|
.la = {
|
|
.reg = 0x374,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x47,
|
|
.name = "ispwb",
|
|
.swgroup = TEGRA_SWGROUP_ISP2,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 7,
|
|
},
|
|
.la = {
|
|
.reg = 0x374,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x4a,
|
|
.name = "xusb_hostr",
|
|
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 10,
|
|
},
|
|
.la = {
|
|
.reg = 0x37c,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x39,
|
|
},
|
|
}, {
|
|
.id = 0x4b,
|
|
.name = "xusb_hostw",
|
|
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 11,
|
|
},
|
|
.la = {
|
|
.reg = 0x37c,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x4c,
|
|
.name = "xusb_devr",
|
|
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 12,
|
|
},
|
|
.la = {
|
|
.reg = 0x380,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x39,
|
|
},
|
|
}, {
|
|
.id = 0x4d,
|
|
.name = "xusb_devw",
|
|
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 13,
|
|
},
|
|
.la = {
|
|
.reg = 0x380,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x4e,
|
|
.name = "isprab",
|
|
.swgroup = TEGRA_SWGROUP_ISP2B,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 14,
|
|
},
|
|
.la = {
|
|
.reg = 0x384,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x18,
|
|
},
|
|
}, {
|
|
.id = 0x50,
|
|
.name = "ispwab",
|
|
.swgroup = TEGRA_SWGROUP_ISP2B,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 16,
|
|
},
|
|
.la = {
|
|
.reg = 0x388,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x51,
|
|
.name = "ispwbb",
|
|
.swgroup = TEGRA_SWGROUP_ISP2B,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 17,
|
|
},
|
|
.la = {
|
|
.reg = 0x388,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x54,
|
|
.name = "tsecsrd",
|
|
.swgroup = TEGRA_SWGROUP_TSEC,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 20,
|
|
},
|
|
.la = {
|
|
.reg = 0x390,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x9b,
|
|
},
|
|
}, {
|
|
.id = 0x55,
|
|
.name = "tsecswr",
|
|
.swgroup = TEGRA_SWGROUP_TSEC,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 21,
|
|
},
|
|
.la = {
|
|
.reg = 0x390,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x56,
|
|
.name = "a9avpscr",
|
|
.swgroup = TEGRA_SWGROUP_A9AVP,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 22,
|
|
},
|
|
.la = {
|
|
.reg = 0x3a4,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x04,
|
|
},
|
|
}, {
|
|
.id = 0x57,
|
|
.name = "a9avpscw",
|
|
.swgroup = TEGRA_SWGROUP_A9AVP,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 23,
|
|
},
|
|
.la = {
|
|
.reg = 0x3a4,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x58,
|
|
.name = "gpusrd",
|
|
.swgroup = TEGRA_SWGROUP_GPU,
|
|
.smmu = {
|
|
/* read-only */
|
|
.reg = 0x230,
|
|
.bit = 24,
|
|
},
|
|
.la = {
|
|
.reg = 0x3c8,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x1a,
|
|
},
|
|
}, {
|
|
.id = 0x59,
|
|
.name = "gpuswr",
|
|
.swgroup = TEGRA_SWGROUP_GPU,
|
|
.smmu = {
|
|
/* read-only */
|
|
.reg = 0x230,
|
|
.bit = 25,
|
|
},
|
|
.la = {
|
|
.reg = 0x3c8,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x5a,
|
|
.name = "displayt",
|
|
.swgroup = TEGRA_SWGROUP_DC,
|
|
.smmu = {
|
|
.reg = 0x230,
|
|
.bit = 26,
|
|
},
|
|
.la = {
|
|
.reg = 0x2f0,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x50,
|
|
},
|
|
}, {
|
|
.id = 0x60,
|
|
.name = "sdmmcra",
|
|
.swgroup = TEGRA_SWGROUP_SDMMC1A,
|
|
.smmu = {
|
|
.reg = 0x234,
|
|
.bit = 0,
|
|
},
|
|
.la = {
|
|
.reg = 0x3b8,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x49,
|
|
},
|
|
}, {
|
|
.id = 0x61,
|
|
.name = "sdmmcraa",
|
|
.swgroup = TEGRA_SWGROUP_SDMMC2A,
|
|
.smmu = {
|
|
.reg = 0x234,
|
|
.bit = 1,
|
|
},
|
|
.la = {
|
|
.reg = 0x3bc,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x49,
|
|
},
|
|
}, {
|
|
.id = 0x62,
|
|
.name = "sdmmcr",
|
|
.swgroup = TEGRA_SWGROUP_SDMMC3A,
|
|
.smmu = {
|
|
.reg = 0x234,
|
|
.bit = 2,
|
|
},
|
|
.la = {
|
|
.reg = 0x3c0,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x49,
|
|
},
|
|
}, {
|
|
.id = 0x63,
|
|
.swgroup = TEGRA_SWGROUP_SDMMC4A,
|
|
.name = "sdmmcrab",
|
|
.smmu = {
|
|
.reg = 0x234,
|
|
.bit = 3,
|
|
},
|
|
.la = {
|
|
.reg = 0x3c4,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x49,
|
|
},
|
|
}, {
|
|
.id = 0x64,
|
|
.name = "sdmmcwa",
|
|
.swgroup = TEGRA_SWGROUP_SDMMC1A,
|
|
.smmu = {
|
|
.reg = 0x234,
|
|
.bit = 4,
|
|
},
|
|
.la = {
|
|
.reg = 0x3b8,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x65,
|
|
.name = "sdmmcwaa",
|
|
.swgroup = TEGRA_SWGROUP_SDMMC2A,
|
|
.smmu = {
|
|
.reg = 0x234,
|
|
.bit = 5,
|
|
},
|
|
.la = {
|
|
.reg = 0x3bc,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x66,
|
|
.name = "sdmmcw",
|
|
.swgroup = TEGRA_SWGROUP_SDMMC3A,
|
|
.smmu = {
|
|
.reg = 0x234,
|
|
.bit = 6,
|
|
},
|
|
.la = {
|
|
.reg = 0x3c0,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x67,
|
|
.name = "sdmmcwab",
|
|
.swgroup = TEGRA_SWGROUP_SDMMC4A,
|
|
.smmu = {
|
|
.reg = 0x234,
|
|
.bit = 7,
|
|
},
|
|
.la = {
|
|
.reg = 0x3c4,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x6c,
|
|
.name = "vicsrd",
|
|
.swgroup = TEGRA_SWGROUP_VIC,
|
|
.smmu = {
|
|
.reg = 0x234,
|
|
.bit = 12,
|
|
},
|
|
.la = {
|
|
.reg = 0x394,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x1a,
|
|
},
|
|
}, {
|
|
.id = 0x6d,
|
|
.name = "vicswr",
|
|
.swgroup = TEGRA_SWGROUP_VIC,
|
|
.smmu = {
|
|
.reg = 0x234,
|
|
.bit = 13,
|
|
},
|
|
.la = {
|
|
.reg = 0x394,
|
|
.shift = 16,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x72,
|
|
.name = "viw",
|
|
.swgroup = TEGRA_SWGROUP_VI,
|
|
.smmu = {
|
|
.reg = 0x234,
|
|
.bit = 18,
|
|
},
|
|
.la = {
|
|
.reg = 0x398,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x80,
|
|
},
|
|
}, {
|
|
.id = 0x73,
|
|
.name = "displayd",
|
|
.swgroup = TEGRA_SWGROUP_DC,
|
|
.smmu = {
|
|
.reg = 0x234,
|
|
.bit = 19,
|
|
},
|
|
.la = {
|
|
.reg = 0x3c8,
|
|
.shift = 0,
|
|
.mask = 0xff,
|
|
.def = 0x50,
|
|
},
|
|
},
|
|
};
|
|
|
|
static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
|
|
{ .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
|
|
{ .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
|
|
{ .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
|
|
{ .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
|
|
{ .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
|
|
{ .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
|
|
{ .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
|
|
{ .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
|
|
{ .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
|
|
{ .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
|
|
{ .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
|
|
{ .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
|
|
{ .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
|
|
{ .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
|
|
{ .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
|
|
{ .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
|
|
{ .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
|
|
{ .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
|
|
{ .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
|
|
{ .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
|
|
{ .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
|
|
{ .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
|
|
{ .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
|
|
};
|
|
|
|
#ifdef CONFIG_ARCH_TEGRA_124_SOC
|
|
static void tegra124_flush_dcache(struct page *page, unsigned long offset,
|
|
size_t size)
|
|
{
|
|
phys_addr_t phys = page_to_phys(page) + offset;
|
|
void *virt = page_address(page) + offset;
|
|
|
|
__cpuc_flush_dcache_area(virt, size);
|
|
outer_flush_range(phys, phys + size);
|
|
}
|
|
|
|
static const struct tegra_smmu_ops tegra124_smmu_ops = {
|
|
.flush_dcache = tegra124_flush_dcache,
|
|
};
|
|
|
|
static const struct tegra_smmu_soc tegra124_smmu_soc = {
|
|
.clients = tegra124_mc_clients,
|
|
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
|
|
.swgroups = tegra124_swgroups,
|
|
.num_swgroups = ARRAY_SIZE(tegra124_swgroups),
|
|
.supports_round_robin_arbitration = true,
|
|
.supports_request_limit = true,
|
|
.num_asids = 128,
|
|
.ops = &tegra124_smmu_ops,
|
|
};
|
|
|
|
const struct tegra_mc_soc tegra124_mc_soc = {
|
|
.clients = tegra124_mc_clients,
|
|
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
|
|
.num_address_bits = 34,
|
|
.atom_size = 32,
|
|
.smmu = &tegra124_smmu_soc,
|
|
.emem_regs = tegra124_mc_emem_regs,
|
|
.num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
|
|
};
|
|
#endif /* CONFIG_ARCH_TEGRA_124_SOC */
|