mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 00:46:39 +07:00
6dc73964fa
The rate for auxclk is 22.59792 by default. Signed-off-by: Tony Lindgren <tony@atomide.com>
159 lines
3.4 KiB
Plaintext
159 lines
3.4 KiB
Plaintext
/*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
&pllss_clocks {
|
|
timer1_fck: timer1_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
|
|
&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
|
|
ti,bit-shift = <3>;
|
|
reg = <0x2e0>;
|
|
};
|
|
|
|
timer2_fck: timer2_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
|
|
&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
|
|
ti,bit-shift = <6>;
|
|
reg = <0x2e0>;
|
|
};
|
|
|
|
sysclk18_ck: sysclk18_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
|
|
ti,bit-shift = <0>;
|
|
reg = <0x02f0>;
|
|
};
|
|
};
|
|
|
|
&scm_clocks {
|
|
devosc_ck: devosc_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
|
|
ti,bit-shift = <21>;
|
|
reg = <0x0040>;
|
|
};
|
|
|
|
/* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */
|
|
auxosc_ck: auxosc_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <22572900>;
|
|
};
|
|
|
|
/* Optional 32768Hz crystal or clock on RTCOSC pins */
|
|
rtcosc_ck: rtcosc_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
/* Optional external clock on TCLKIN pin, set rate in baord dts file */
|
|
tclkin_ck: tclkin_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
virt_20000000_ck: virt_20000000_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <20000000>;
|
|
};
|
|
|
|
virt_19200000_ck: virt_19200000_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
mpu_ck: mpu_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000000000>;
|
|
};
|
|
|
|
sysclk4_ck: sysclk4_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <222000000>;
|
|
};
|
|
|
|
sysclk6_ck: sysclk6_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <100000000>;
|
|
};
|
|
|
|
sysclk10_ck: sysclk10_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <125000000>;
|
|
};
|
|
|
|
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <250000000>;
|
|
};
|
|
|
|
};
|
|
|
|
&prcm_clocks {
|
|
osc_src_ck: osc_src_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&devosc_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <1>;
|
|
};
|
|
|
|
mpu_clksrc_ck: mpu_clksrc_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&devosc_ck>, <&rtcdivider_ck>;
|
|
ti,bit-shift = <0>;
|
|
reg = <0x0040>;
|
|
};
|
|
|
|
/* Fixed divider clock 0.0016384 * devosc */
|
|
rtcdivider_ck: rtcdivider_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&devosc_ck>;
|
|
clock-mult = <128>;
|
|
clock-div = <78125>;
|
|
};
|
|
|
|
aud_clkin0_ck: aud_clkin0_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <20000000>;
|
|
};
|
|
|
|
aud_clkin1_ck: aud_clkin1_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <20000000>;
|
|
};
|
|
|
|
aud_clkin2_ck: aud_clkin2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <20000000>;
|
|
};
|
|
};
|