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3d49538364
The omap3_pmx_core pinmux device in the device tree handles the system controller module (SCM) PADCONFS fonction. Its control registers are split in two distinct areas, with other SCM registers in-between. Those other registers can't thus be requested by other drivers as the memory region gets reserved by the pinmux driver. Split the omap3_pmx_core device tree node in two for the two memory regions. The second region address and size depends on the SoC model. The change in omap3.dtsi fixes an "external abort on non-linefetch" when doing cat /sys/kernel/debug/pinctrl/.../pins on a Nokia N900. Note that the core2 padconf region is different for 3430 vs 3630, and does not exist on 3517 as noted by Nishanth Menon <nm@ti.com>. Reported-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-By: Sebastian Reichel <sre@debian.org> Signed-off-by: Nishanth Menon <nm@ti.com> [tony@atomide.com: updated for 3430 vs 3630 core2 based on Nishant's patch] Signed-off-by: Tony Lindgren <tony@atomide.com>
42 lines
948 B
Plaintext
42 lines
948 B
Plaintext
/*
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* Device Tree Source for OMAP34xx/OMAP35xx SoC
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include "omap3.dtsi"
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/ {
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cpus {
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cpu@0 {
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/* OMAP343x/OMAP35xx variants OPP1-5 */
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operating-points = <
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/* kHz uV */
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125000 975000
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250000 1075000
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500000 1200000
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550000 1270000
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600000 1350000
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>;
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clock-latency = <300000>; /* From legacy driver */
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};
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};
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ocp {
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omap3_pmx_core2: pinmux@480025d8 {
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compatible = "ti,omap3-padconf", "pinctrl-single";
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reg = <0x480025d8 0x24>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xff1f>;
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};
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};
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};
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