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Document APMU and SMP enable method for RZ/G1N (R8A7744) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
36 lines
1.1 KiB
Plaintext
36 lines
1.1 KiB
Plaintext
DT bindings for the Renesas Advanced Power Management Unit
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Renesas R-Car and RZ/G1 SoCs utilize one or more APMU hardware units
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for CPU core power domain control including SMP boot and CPU Hotplug.
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Required properties:
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- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
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Examples with soctypes are:
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- "renesas,r8a7743-apmu" (RZ/G1M)
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- "renesas,r8a7744-apmu" (RZ/G1N)
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- "renesas,r8a7745-apmu" (RZ/G1E)
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- "renesas,r8a77470-apmu" (RZ/G1C)
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- "renesas,r8a7790-apmu" (R-Car H2)
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- "renesas,r8a7791-apmu" (R-Car M2-W)
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- "renesas,r8a7792-apmu" (R-Car V2H)
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- "renesas,r8a7793-apmu" (R-Car M2-N)
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- "renesas,r8a7794-apmu" (R-Car E2)
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- reg: Base address and length of the I/O registers used by the APMU.
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- cpus: This node contains a list of CPU cores, which should match the order
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of CPU cores used by the WUPCR and PSTR registers in the Advanced Power
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Management Unit section of the device's datasheet.
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Example:
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This shows the r8a7791 APMU that can control CPU0 and CPU1.
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apmu@e6152000 {
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compatible = "renesas,r8a7791-apmu", "renesas,apmu";
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reg = <0 0xe6152000 0 0x188>;
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cpus = <&cpu0 &cpu1>;
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};
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