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82dfbd27c8
Update DT documentation to include optional PHYs for cadence PCIe host and endpoint controllers. Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
28 lines
978 B
Plaintext
28 lines
978 B
Plaintext
* Cadence PCIe endpoint controller
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Required properties:
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- compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used.
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- reg: Should contain the controller register base address and AXI interface
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region base address respectively.
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- reg-names: Must be "reg" and "mem" respectively.
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- cdns,max-outbound-regions: Set to maximum number of outbound regions
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Optional properties:
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- max-functions: Maximum number of functions that can be configured (default 1).
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- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
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than one in the list. If only one PHY listed it must manage all lanes.
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- phy-names: List of names to identify the PHY.
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Example:
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pcie@fc000000 {
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compatible = "cdns,cdns-pcie-ep";
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reg = <0x0 0xfc000000 0x0 0x01000000>,
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<0x0 0x80000000 0x0 0x40000000>;
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reg-names = "reg", "mem";
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cdns,max-outbound-regions = <16>;
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max-functions = /bits/ 8 <8>;
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phys = <&ep_phy0 &ep_phy1>;
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phy-names = "pcie-lane0","pcie-lane1";
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};
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