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c22c2c6008
This is a simple move of all header files that are no longer included by anything else from the include/mach directory to the platform directory itself as preparation for multiplatform support. The mach/uncompress.h headers are left in place for now, and are mildly modified to be independent of the other headers. They will be removed entirely when ARCH_MULTIPLATFORM gets enabled and they become obsolete. Rather than updating the path names inside of the comments of each header, I delete those comments to avoid having to update them again, should they get moved or copied another time. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
292 lines
7.4 KiB
C
292 lines
7.4 KiB
C
/*
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* arch/arm/mach-orion5x/rd88f5182-setup.c
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*
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* Marvell Orion-NAS Reference Design Setup
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*
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* Maintainer: Ronen Shitrit <rshitrit@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/gpio.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/ata_platform.h>
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#include <linux/i2c.h>
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#include <linux/leds.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/pci.h>
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#include "common.h"
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#include "mpp.h"
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#include "orion5x.h"
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/*****************************************************************************
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* RD-88F5182 Info
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****************************************************************************/
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/*
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* 512K NOR flash Device bus boot chip select
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*/
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#define RD88F5182_NOR_BOOT_BASE 0xf4000000
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#define RD88F5182_NOR_BOOT_SIZE SZ_512K
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/*
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* 16M NOR flash on Device bus chip select 1
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*/
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#define RD88F5182_NOR_BASE 0xfc000000
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#define RD88F5182_NOR_SIZE SZ_16M
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/*
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* PCI
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*/
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#define RD88F5182_PCI_SLOT0_OFFS 7
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#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
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#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
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/*****************************************************************************
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* 16M NOR Flash on Device bus CS1
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****************************************************************************/
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static struct physmap_flash_data rd88f5182_nor_flash_data = {
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.width = 1,
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};
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static struct resource rd88f5182_nor_flash_resource = {
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.flags = IORESOURCE_MEM,
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.start = RD88F5182_NOR_BASE,
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.end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
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};
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static struct platform_device rd88f5182_nor_flash = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &rd88f5182_nor_flash_data,
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},
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.num_resources = 1,
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.resource = &rd88f5182_nor_flash_resource,
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};
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/*****************************************************************************
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* Use GPIO LED as CPU active indication
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****************************************************************************/
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#define RD88F5182_GPIO_LED 0
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static struct gpio_led rd88f5182_gpio_led_pins[] = {
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{
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.name = "rd88f5182:cpu",
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.default_trigger = "cpu0",
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.gpio = RD88F5182_GPIO_LED,
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},
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};
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static struct gpio_led_platform_data rd88f5182_gpio_led_data = {
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.leds = rd88f5182_gpio_led_pins,
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.num_leds = ARRAY_SIZE(rd88f5182_gpio_led_pins),
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};
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static struct platform_device rd88f5182_gpio_leds = {
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.name = "leds-gpio",
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.id = -1,
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.dev = {
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.platform_data = &rd88f5182_gpio_led_data,
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},
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};
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/*****************************************************************************
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* PCI
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****************************************************************************/
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static void __init rd88f5182_pci_preinit(void)
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{
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int pin;
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/*
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* Configure PCI GPIO IRQ pins
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*/
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pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
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if (gpio_request(pin, "PCI IntA") == 0) {
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if (gpio_direction_input(pin) == 0) {
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irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit failed to "
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"set_irq_type pin %d\n", pin);
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gpio_free(pin);
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}
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
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}
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pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
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if (gpio_request(pin, "PCI IntB") == 0) {
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if (gpio_direction_input(pin) == 0) {
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irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit failed to "
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"set_irq_type pin %d\n", pin);
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gpio_free(pin);
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}
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
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}
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}
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static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
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u8 pin)
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{
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int irq;
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/*
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* Check for devices with hard-wired IRQs.
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*/
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irq = orion5x_pci_map_irq(dev, slot, pin);
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if (irq != -1)
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return irq;
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/*
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* PCI IRQs are connected via GPIOs
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*/
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switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
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case 0:
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if (pin == 1)
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return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
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else
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return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
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default:
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return -1;
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}
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}
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static struct hw_pci rd88f5182_pci __initdata = {
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.nr_controllers = 2,
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.preinit = rd88f5182_pci_preinit,
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.setup = orion5x_pci_sys_setup,
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.scan = orion5x_pci_sys_scan_bus,
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.map_irq = rd88f5182_pci_map_irq,
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};
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static int __init rd88f5182_pci_init(void)
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{
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if (machine_is_rd88f5182())
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pci_common_init(&rd88f5182_pci);
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return 0;
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}
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subsys_initcall(rd88f5182_pci_init);
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/*****************************************************************************
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* Ethernet
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****************************************************************************/
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static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
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.phy_addr = MV643XX_ETH_PHY_ADDR(8),
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};
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/*****************************************************************************
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* RTC DS1338 on I2C bus
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****************************************************************************/
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static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
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I2C_BOARD_INFO("ds1338", 0x68),
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};
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/*****************************************************************************
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* Sata
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****************************************************************************/
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static struct mv_sata_platform_data rd88f5182_sata_data = {
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.n_ports = 2,
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};
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/*****************************************************************************
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* General Setup
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****************************************************************************/
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static unsigned int rd88f5182_mpp_modes[] __initdata = {
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MPP0_GPIO, /* Debug Led */
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MPP1_GPIO, /* Reset Switch */
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MPP2_UNUSED,
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MPP3_GPIO, /* RTC Int */
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MPP4_GPIO,
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MPP5_GPIO,
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MPP6_GPIO, /* PCI_intA */
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MPP7_GPIO, /* PCI_intB */
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MPP8_UNUSED,
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MPP9_UNUSED,
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MPP10_UNUSED,
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MPP11_UNUSED,
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MPP12_SATA_LED, /* SATA 0 presence */
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MPP13_SATA_LED, /* SATA 1 presence */
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MPP14_SATA_LED, /* SATA 0 active */
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MPP15_SATA_LED, /* SATA 1 active */
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MPP16_UNUSED,
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MPP17_UNUSED,
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MPP18_UNUSED,
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MPP19_UNUSED,
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0,
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};
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static void __init rd88f5182_init(void)
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{
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/*
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* Setup basic Orion functions. Need to be called early.
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*/
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orion5x_init();
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orion5x_mpp_conf(rd88f5182_mpp_modes);
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/*
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* MPP[20] PCI Clock to MV88F5182
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* MPP[21] PCI Clock to mini PCI CON11
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* MPP[22] USB 0 over current indication
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* MPP[23] USB 1 over current indication
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* MPP[24] USB 1 over current enable
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* MPP[25] USB 0 over current enable
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*/
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/*
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* Configure peripherals.
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*/
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orion5x_ehci0_init();
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orion5x_ehci1_init();
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orion5x_eth_init(&rd88f5182_eth_data);
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orion5x_i2c_init();
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orion5x_sata_init(&rd88f5182_sata_data);
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orion5x_uart0_init();
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orion5x_xor_init();
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
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ORION_MBUS_DEVBUS_BOOT_ATTR,
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RD88F5182_NOR_BOOT_BASE,
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RD88F5182_NOR_BOOT_SIZE);
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
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ORION_MBUS_DEVBUS_ATTR(1),
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RD88F5182_NOR_BASE,
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RD88F5182_NOR_SIZE);
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platform_device_register(&rd88f5182_nor_flash);
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platform_device_register(&rd88f5182_gpio_leds);
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i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
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}
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MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
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/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
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.atag_offset = 0x100,
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.nr_irqs = ORION5X_NR_IRQS,
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.init_machine = rd88f5182_init,
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.map_io = orion5x_map_io,
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.init_early = orion5x_init_early,
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.init_irq = orion5x_init_irq,
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.init_time = orion5x_timer_init,
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.restart = orion5x_restart,
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MACHINE_END
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