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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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3d03137864
Driver needs ZynqMP firmware interface to call EEMI APIs. In case firmware is not ready, dependent drivers should wait until the firmware is ready. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
301 lines
7.6 KiB
C
301 lines
7.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Xilinx Zynq MPSoC Firmware layer
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*
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* Copyright (C) 2014-2018 Xilinx
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*
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* Michal Simek <michal.simek@xilinx.com>
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* Davorin Mista <davorin.mista@aggios.com>
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* Jolly Shah <jollys@xilinx.com>
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* Rajan Vaja <rajanv@xilinx.com>
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*/
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#ifndef __FIRMWARE_ZYNQMP_H__
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#define __FIRMWARE_ZYNQMP_H__
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#define ZYNQMP_PM_VERSION_MAJOR 1
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#define ZYNQMP_PM_VERSION_MINOR 0
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#define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
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ZYNQMP_PM_VERSION_MINOR)
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#define ZYNQMP_TZ_VERSION_MAJOR 1
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#define ZYNQMP_TZ_VERSION_MINOR 0
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#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
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ZYNQMP_TZ_VERSION_MINOR)
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/* SMC SIP service Call Function Identifier Prefix */
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#define PM_SIP_SVC 0xC2000000
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#define PM_GET_TRUSTZONE_VERSION 0xa03
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#define PM_SET_SUSPEND_MODE 0xa02
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#define GET_CALLBACK_DATA 0xa01
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/* Number of 32bits values in payload */
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#define PAYLOAD_ARG_CNT 4U
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/* Number of arguments for a callback */
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#define CB_ARG_CNT 4
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/* Payload size (consists of callback API ID + arguments) */
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#define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
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#define ZYNQMP_PM_MAX_QOS 100U
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/* Node capabilities */
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#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
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#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
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#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
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#define ZYNQMP_PM_CAPABILITY_POWER 0x8U
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enum pm_api_id {
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PM_GET_API_VERSION = 1,
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PM_REQUEST_NODE = 13,
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PM_RELEASE_NODE,
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PM_SET_REQUIREMENT,
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PM_RESET_ASSERT = 17,
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PM_RESET_GET_STATUS,
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PM_PM_INIT_FINALIZE = 21,
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PM_GET_CHIPID = 24,
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PM_IOCTL = 34,
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PM_QUERY_DATA,
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PM_CLOCK_ENABLE,
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PM_CLOCK_DISABLE,
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PM_CLOCK_GETSTATE,
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PM_CLOCK_SETDIVIDER,
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PM_CLOCK_GETDIVIDER,
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PM_CLOCK_SETRATE,
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PM_CLOCK_GETRATE,
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PM_CLOCK_SETPARENT,
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PM_CLOCK_GETPARENT,
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};
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/* PMU-FW return status codes */
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enum pm_ret_status {
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XST_PM_SUCCESS = 0,
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XST_PM_INTERNAL = 2000,
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XST_PM_CONFLICT,
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XST_PM_NO_ACCESS,
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XST_PM_INVALID_NODE,
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XST_PM_DOUBLE_REQ,
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XST_PM_ABORT_SUSPEND,
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};
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enum pm_ioctl_id {
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IOCTL_SET_PLL_FRAC_MODE = 8,
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IOCTL_GET_PLL_FRAC_MODE,
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IOCTL_SET_PLL_FRAC_DATA,
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IOCTL_GET_PLL_FRAC_DATA,
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};
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enum pm_query_id {
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PM_QID_INVALID,
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PM_QID_CLOCK_GET_NAME,
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PM_QID_CLOCK_GET_TOPOLOGY,
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PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
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PM_QID_CLOCK_GET_PARENTS,
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PM_QID_CLOCK_GET_ATTRIBUTES,
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PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
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};
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enum zynqmp_pm_reset_action {
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PM_RESET_ACTION_RELEASE,
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PM_RESET_ACTION_ASSERT,
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PM_RESET_ACTION_PULSE,
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};
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enum zynqmp_pm_reset {
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ZYNQMP_PM_RESET_START = 1000,
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ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
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ZYNQMP_PM_RESET_PCIE_BRIDGE,
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ZYNQMP_PM_RESET_PCIE_CTRL,
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ZYNQMP_PM_RESET_DP,
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ZYNQMP_PM_RESET_SWDT_CRF,
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ZYNQMP_PM_RESET_AFI_FM5,
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ZYNQMP_PM_RESET_AFI_FM4,
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ZYNQMP_PM_RESET_AFI_FM3,
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ZYNQMP_PM_RESET_AFI_FM2,
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ZYNQMP_PM_RESET_AFI_FM1,
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ZYNQMP_PM_RESET_AFI_FM0,
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ZYNQMP_PM_RESET_GDMA,
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ZYNQMP_PM_RESET_GPU_PP1,
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ZYNQMP_PM_RESET_GPU_PP0,
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ZYNQMP_PM_RESET_GPU,
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ZYNQMP_PM_RESET_GT,
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ZYNQMP_PM_RESET_SATA,
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ZYNQMP_PM_RESET_ACPU3_PWRON,
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ZYNQMP_PM_RESET_ACPU2_PWRON,
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ZYNQMP_PM_RESET_ACPU1_PWRON,
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ZYNQMP_PM_RESET_ACPU0_PWRON,
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ZYNQMP_PM_RESET_APU_L2,
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ZYNQMP_PM_RESET_ACPU3,
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ZYNQMP_PM_RESET_ACPU2,
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ZYNQMP_PM_RESET_ACPU1,
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ZYNQMP_PM_RESET_ACPU0,
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ZYNQMP_PM_RESET_DDR,
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ZYNQMP_PM_RESET_APM_FPD,
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ZYNQMP_PM_RESET_SOFT,
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ZYNQMP_PM_RESET_GEM0,
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ZYNQMP_PM_RESET_GEM1,
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ZYNQMP_PM_RESET_GEM2,
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ZYNQMP_PM_RESET_GEM3,
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ZYNQMP_PM_RESET_QSPI,
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ZYNQMP_PM_RESET_UART0,
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ZYNQMP_PM_RESET_UART1,
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ZYNQMP_PM_RESET_SPI0,
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ZYNQMP_PM_RESET_SPI1,
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ZYNQMP_PM_RESET_SDIO0,
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ZYNQMP_PM_RESET_SDIO1,
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ZYNQMP_PM_RESET_CAN0,
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ZYNQMP_PM_RESET_CAN1,
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ZYNQMP_PM_RESET_I2C0,
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ZYNQMP_PM_RESET_I2C1,
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ZYNQMP_PM_RESET_TTC0,
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ZYNQMP_PM_RESET_TTC1,
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ZYNQMP_PM_RESET_TTC2,
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ZYNQMP_PM_RESET_TTC3,
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ZYNQMP_PM_RESET_SWDT_CRL,
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ZYNQMP_PM_RESET_NAND,
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ZYNQMP_PM_RESET_ADMA,
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ZYNQMP_PM_RESET_GPIO,
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ZYNQMP_PM_RESET_IOU_CC,
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ZYNQMP_PM_RESET_TIMESTAMP,
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ZYNQMP_PM_RESET_RPU_R50,
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ZYNQMP_PM_RESET_RPU_R51,
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ZYNQMP_PM_RESET_RPU_AMBA,
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ZYNQMP_PM_RESET_OCM,
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ZYNQMP_PM_RESET_RPU_PGE,
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ZYNQMP_PM_RESET_USB0_CORERESET,
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ZYNQMP_PM_RESET_USB1_CORERESET,
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ZYNQMP_PM_RESET_USB0_HIBERRESET,
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ZYNQMP_PM_RESET_USB1_HIBERRESET,
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ZYNQMP_PM_RESET_USB0_APB,
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ZYNQMP_PM_RESET_USB1_APB,
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ZYNQMP_PM_RESET_IPI,
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ZYNQMP_PM_RESET_APM_LPD,
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ZYNQMP_PM_RESET_RTC,
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ZYNQMP_PM_RESET_SYSMON,
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ZYNQMP_PM_RESET_AFI_FM6,
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ZYNQMP_PM_RESET_LPD_SWDT,
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ZYNQMP_PM_RESET_FPD,
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ZYNQMP_PM_RESET_RPU_DBG1,
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ZYNQMP_PM_RESET_RPU_DBG0,
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ZYNQMP_PM_RESET_DBG_LPD,
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ZYNQMP_PM_RESET_DBG_FPD,
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ZYNQMP_PM_RESET_APLL,
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ZYNQMP_PM_RESET_DPLL,
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ZYNQMP_PM_RESET_VPLL,
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ZYNQMP_PM_RESET_IOPLL,
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ZYNQMP_PM_RESET_RPLL,
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ZYNQMP_PM_RESET_GPO3_PL_0,
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ZYNQMP_PM_RESET_GPO3_PL_1,
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ZYNQMP_PM_RESET_GPO3_PL_2,
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ZYNQMP_PM_RESET_GPO3_PL_3,
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ZYNQMP_PM_RESET_GPO3_PL_4,
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ZYNQMP_PM_RESET_GPO3_PL_5,
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ZYNQMP_PM_RESET_GPO3_PL_6,
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ZYNQMP_PM_RESET_GPO3_PL_7,
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ZYNQMP_PM_RESET_GPO3_PL_8,
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ZYNQMP_PM_RESET_GPO3_PL_9,
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ZYNQMP_PM_RESET_GPO3_PL_10,
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ZYNQMP_PM_RESET_GPO3_PL_11,
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ZYNQMP_PM_RESET_GPO3_PL_12,
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ZYNQMP_PM_RESET_GPO3_PL_13,
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ZYNQMP_PM_RESET_GPO3_PL_14,
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ZYNQMP_PM_RESET_GPO3_PL_15,
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ZYNQMP_PM_RESET_GPO3_PL_16,
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ZYNQMP_PM_RESET_GPO3_PL_17,
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ZYNQMP_PM_RESET_GPO3_PL_18,
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ZYNQMP_PM_RESET_GPO3_PL_19,
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ZYNQMP_PM_RESET_GPO3_PL_20,
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ZYNQMP_PM_RESET_GPO3_PL_21,
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ZYNQMP_PM_RESET_GPO3_PL_22,
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ZYNQMP_PM_RESET_GPO3_PL_23,
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ZYNQMP_PM_RESET_GPO3_PL_24,
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ZYNQMP_PM_RESET_GPO3_PL_25,
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ZYNQMP_PM_RESET_GPO3_PL_26,
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ZYNQMP_PM_RESET_GPO3_PL_27,
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ZYNQMP_PM_RESET_GPO3_PL_28,
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ZYNQMP_PM_RESET_GPO3_PL_29,
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ZYNQMP_PM_RESET_GPO3_PL_30,
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ZYNQMP_PM_RESET_GPO3_PL_31,
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ZYNQMP_PM_RESET_RPU_LS,
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ZYNQMP_PM_RESET_PS_ONLY,
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ZYNQMP_PM_RESET_PL,
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ZYNQMP_PM_RESET_PS_PL0,
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ZYNQMP_PM_RESET_PS_PL1,
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ZYNQMP_PM_RESET_PS_PL2,
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ZYNQMP_PM_RESET_PS_PL3,
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ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
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};
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enum zynqmp_pm_suspend_reason {
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SUSPEND_POWER_REQUEST = 201,
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SUSPEND_ALERT,
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SUSPEND_SYSTEM_SHUTDOWN,
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};
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enum zynqmp_pm_request_ack {
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ZYNQMP_PM_REQUEST_ACK_NO = 1,
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ZYNQMP_PM_REQUEST_ACK_BLOCKING,
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ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
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};
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/**
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* struct zynqmp_pm_query_data - PM query data
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* @qid: query ID
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* @arg1: Argument 1 of query data
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* @arg2: Argument 2 of query data
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* @arg3: Argument 3 of query data
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*/
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struct zynqmp_pm_query_data {
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u32 qid;
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u32 arg1;
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u32 arg2;
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u32 arg3;
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};
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struct zynqmp_eemi_ops {
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int (*get_api_version)(u32 *version);
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int (*get_chipid)(u32 *idcode, u32 *version);
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int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
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int (*clock_enable)(u32 clock_id);
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int (*clock_disable)(u32 clock_id);
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int (*clock_getstate)(u32 clock_id, u32 *state);
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int (*clock_setdivider)(u32 clock_id, u32 divider);
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int (*clock_getdivider)(u32 clock_id, u32 *divider);
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int (*clock_setrate)(u32 clock_id, u64 rate);
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int (*clock_getrate)(u32 clock_id, u64 *rate);
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int (*clock_setparent)(u32 clock_id, u32 parent_id);
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int (*clock_getparent)(u32 clock_id, u32 *parent_id);
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int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
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int (*reset_assert)(const enum zynqmp_pm_reset reset,
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const enum zynqmp_pm_reset_action assert_flag);
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int (*reset_get_status)(const enum zynqmp_pm_reset reset, u32 *status);
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int (*init_finalize)(void);
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int (*set_suspend_mode)(u32 mode);
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int (*request_node)(const u32 node,
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const u32 capabilities,
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const u32 qos,
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const enum zynqmp_pm_request_ack ack);
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int (*release_node)(const u32 node);
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int (*set_requirement)(const u32 node,
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const u32 capabilities,
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const u32 qos,
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const enum zynqmp_pm_request_ack ack);
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};
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int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
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u32 arg2, u32 arg3, u32 *ret_payload);
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#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
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const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
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#else
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static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
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{
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return ERR_PTR(-ENODEV);
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}
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#endif
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#endif /* __FIRMWARE_ZYNQMP_H__ */
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