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f43194c144
Marvell PPv2.2 controller present on CP-110 need the extra "mg_core_clk"
clock to avoid system hangs when powering some network interfaces up.
This issue appeared after a recent clock rework on Armada 7K/8K platforms.
This commit adds the new clock and updates the documentation accordingly.
[gregory.clement: use the real first commit to fix and add the cc:stable
flag]
Fixes: e3af9f7c6e ("RM64: dts: marvell: armada-cp110: Fix clock resources for various node")
Cc: <stable@vger.kernel.org>
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
123 lines
3.9 KiB
Plaintext
123 lines
3.9 KiB
Plaintext
* Marvell Armada 375 Ethernet Controller (PPv2.1)
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Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
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Required properties:
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- compatible: should be one of:
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"marvell,armada-375-pp2"
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"marvell,armada-7k-pp2"
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- reg: addresses and length of the register sets for the device.
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For "marvell,armada-375-pp2", must contain the following register
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sets:
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- common controller registers
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- LMS registers
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- one register area per Ethernet port
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For "marvell,armada-7k-pp2", must contain the following register
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sets:
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- packet processor registers
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- networking interfaces registers
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- clocks: pointers to the reference clocks for this device, consequently:
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- main controller clock (for both armada-375-pp2 and armada-7k-pp2)
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- GOP clock (for both armada-375-pp2 and armada-7k-pp2)
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- MG clock (only for armada-7k-pp2)
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- MG Core clock (only for armada-7k-pp2)
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- AXI clock (only for armada-7k-pp2)
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- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk",
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"mg_core_clk" and "axi_clk" (the 3 latter only for armada-7k-pp2).
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The ethernet ports are represented by subnodes. At least one port is
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required.
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Required properties (port):
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- interrupts: interrupt for the port
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- port-id: ID of the port from the MAC point of view
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- gop-port-id: only for marvell,armada-7k-pp2, ID of the port from the
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GOP (Group Of Ports) point of view. This ID is used to index the
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per-port registers in the second register area.
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- phy-mode: See ethernet.txt file in the same directory
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Optional properties (port):
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- marvell,loopback: port is loopback mode
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- phy: a phandle to a phy node defining the PHY address (as the reg
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property, a single integer).
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- interrupt-names: if more than a single interrupt for rx is given, must
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be the name associated to the interrupts listed. Valid
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names are: "tx-cpu0", "tx-cpu1", "tx-cpu2", "tx-cpu3",
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"rx-shared", "link".
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- marvell,system-controller: a phandle to the system controller.
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Example for marvell,armada-375-pp2:
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ethernet@f0000 {
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compatible = "marvell,armada-375-pp2";
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reg = <0xf0000 0xa000>,
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<0xc0000 0x3060>,
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<0xc4000 0x100>,
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<0xc5000 0x100>;
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clocks = <&gateclk 3>, <&gateclk 19>;
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clock-names = "pp_clk", "gop_clk";
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eth0: eth0@c4000 {
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <0>;
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phy = <&phy0>;
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phy-mode = "gmii";
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};
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eth1: eth1@c5000 {
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <1>;
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phy = <&phy3>;
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phy-mode = "gmii";
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};
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};
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Example for marvell,armada-7k-pp2:
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cpm_ethernet: ethernet@0 {
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compatible = "marvell,armada-7k-pp22";
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reg = <0x0 0x100000>, <0x129000 0xb000>;
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clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,
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<&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>;
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clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk";
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eth0: eth0 {
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interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
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"tx-cpu3", "rx-shared";
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port-id = <0>;
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gop-port-id = <0>;
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};
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eth1: eth1 {
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interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
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"tx-cpu3", "rx-shared";
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port-id = <1>;
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gop-port-id = <2>;
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};
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eth2: eth2 {
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interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
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"tx-cpu3", "rx-shared";
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port-id = <2>;
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gop-port-id = <3>;
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};
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};
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