mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 05:14:51 +07:00
997a89003c
We need to be able to prevent memory from being freed while it's still mapped in a GPU's address-space. Will be used by upcoming MMU changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
354 lines
10 KiB
C
354 lines
10 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <engine/falcon.h>
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#include <core/gpuobj.h>
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#include <subdev/timer.h>
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#include <engine/fifo.h>
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static int
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nvkm_falcon_oclass_get(struct nvkm_oclass *oclass, int index)
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{
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struct nvkm_falcon *falcon = nvkm_falcon(oclass->engine);
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int c = 0;
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while (falcon->func->sclass[c].oclass) {
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if (c++ == index) {
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oclass->base = falcon->func->sclass[index];
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return index;
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}
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}
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return c;
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}
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static int
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nvkm_falcon_cclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
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int align, struct nvkm_gpuobj **pgpuobj)
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{
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return nvkm_gpuobj_new(object->engine->subdev.device, 256,
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align, true, parent, pgpuobj);
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}
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static const struct nvkm_object_func
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nvkm_falcon_cclass = {
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.bind = nvkm_falcon_cclass_bind,
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};
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static void
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nvkm_falcon_intr(struct nvkm_engine *engine)
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{
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struct nvkm_falcon *falcon = nvkm_falcon(engine);
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struct nvkm_subdev *subdev = &falcon->engine.subdev;
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struct nvkm_device *device = subdev->device;
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const u32 base = falcon->addr;
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u32 dest = nvkm_rd32(device, base + 0x01c);
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u32 intr = nvkm_rd32(device, base + 0x008) & dest & ~(dest >> 16);
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u32 inst = nvkm_rd32(device, base + 0x050) & 0x3fffffff;
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struct nvkm_fifo_chan *chan;
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unsigned long flags;
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chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags);
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if (intr & 0x00000040) {
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if (falcon->func->intr) {
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falcon->func->intr(falcon, chan);
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nvkm_wr32(device, base + 0x004, 0x00000040);
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intr &= ~0x00000040;
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}
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}
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if (intr & 0x00000010) {
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nvkm_debug(subdev, "ucode halted\n");
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nvkm_wr32(device, base + 0x004, 0x00000010);
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intr &= ~0x00000010;
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}
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if (intr) {
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nvkm_error(subdev, "intr %08x\n", intr);
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nvkm_wr32(device, base + 0x004, intr);
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}
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nvkm_fifo_chan_put(device->fifo, flags, &chan);
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}
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static int
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nvkm_falcon_fini(struct nvkm_engine *engine, bool suspend)
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{
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struct nvkm_falcon *falcon = nvkm_falcon(engine);
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struct nvkm_device *device = falcon->engine.subdev.device;
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const u32 base = falcon->addr;
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if (!suspend) {
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nvkm_memory_unref(&falcon->core);
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if (falcon->external) {
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vfree(falcon->data.data);
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vfree(falcon->code.data);
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falcon->code.data = NULL;
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}
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}
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nvkm_mask(device, base + 0x048, 0x00000003, 0x00000000);
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nvkm_wr32(device, base + 0x014, 0xffffffff);
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return 0;
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}
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static void *
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vmemdup(const void *src, size_t len)
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{
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void *p = vmalloc(len);
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if (p)
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memcpy(p, src, len);
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return p;
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}
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static int
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nvkm_falcon_oneinit(struct nvkm_engine *engine)
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{
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struct nvkm_falcon *falcon = nvkm_falcon(engine);
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struct nvkm_subdev *subdev = &falcon->engine.subdev;
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struct nvkm_device *device = subdev->device;
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const u32 base = falcon->addr;
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u32 caps;
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/* determine falcon capabilities */
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if (device->chipset < 0xa3 ||
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device->chipset == 0xaa || device->chipset == 0xac) {
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falcon->version = 0;
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falcon->secret = (falcon->addr == 0x087000) ? 1 : 0;
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} else {
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caps = nvkm_rd32(device, base + 0x12c);
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falcon->version = (caps & 0x0000000f);
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falcon->secret = (caps & 0x00000030) >> 4;
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}
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caps = nvkm_rd32(device, base + 0x108);
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falcon->code.limit = (caps & 0x000001ff) << 8;
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falcon->data.limit = (caps & 0x0003fe00) >> 1;
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nvkm_debug(subdev, "falcon version: %d\n", falcon->version);
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nvkm_debug(subdev, "secret level: %d\n", falcon->secret);
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nvkm_debug(subdev, "code limit: %d\n", falcon->code.limit);
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nvkm_debug(subdev, "data limit: %d\n", falcon->data.limit);
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return 0;
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}
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static int
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nvkm_falcon_init(struct nvkm_engine *engine)
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{
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struct nvkm_falcon *falcon = nvkm_falcon(engine);
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struct nvkm_subdev *subdev = &falcon->engine.subdev;
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struct nvkm_device *device = subdev->device;
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const struct firmware *fw;
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char name[32] = "internal";
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const u32 base = falcon->addr;
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int ret, i;
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/* wait for 'uc halted' to be signalled before continuing */
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if (falcon->secret && falcon->version < 4) {
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if (!falcon->version) {
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nvkm_msec(device, 2000,
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if (nvkm_rd32(device, base + 0x008) & 0x00000010)
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break;
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);
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} else {
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nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, base + 0x180) & 0x80000000))
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break;
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);
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}
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nvkm_wr32(device, base + 0x004, 0x00000010);
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}
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/* disable all interrupts */
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nvkm_wr32(device, base + 0x014, 0xffffffff);
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/* no default ucode provided by the engine implementation, try and
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* locate a "self-bootstrapping" firmware image for the engine
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*/
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if (!falcon->code.data) {
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snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03x",
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device->chipset, falcon->addr >> 12);
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ret = request_firmware(&fw, name, device->dev);
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if (ret == 0) {
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falcon->code.data = vmemdup(fw->data, fw->size);
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falcon->code.size = fw->size;
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falcon->data.data = NULL;
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falcon->data.size = 0;
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release_firmware(fw);
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}
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falcon->external = true;
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}
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/* next step is to try and load "static code/data segment" firmware
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* images for the engine
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*/
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if (!falcon->code.data) {
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snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xd",
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device->chipset, falcon->addr >> 12);
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ret = request_firmware(&fw, name, device->dev);
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if (ret) {
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nvkm_error(subdev, "unable to load firmware data\n");
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return -ENODEV;
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}
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falcon->data.data = vmemdup(fw->data, fw->size);
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falcon->data.size = fw->size;
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release_firmware(fw);
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if (!falcon->data.data)
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return -ENOMEM;
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snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xc",
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device->chipset, falcon->addr >> 12);
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ret = request_firmware(&fw, name, device->dev);
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if (ret) {
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nvkm_error(subdev, "unable to load firmware code\n");
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return -ENODEV;
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}
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falcon->code.data = vmemdup(fw->data, fw->size);
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falcon->code.size = fw->size;
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release_firmware(fw);
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if (!falcon->code.data)
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return -ENOMEM;
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}
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nvkm_debug(subdev, "firmware: %s (%s)\n", name, falcon->data.data ?
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"static code/data segments" : "self-bootstrapping");
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/* ensure any "self-bootstrapping" firmware image is in vram */
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if (!falcon->data.data && !falcon->core) {
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ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
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falcon->code.size, 256, false,
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&falcon->core);
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if (ret) {
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nvkm_error(subdev, "core allocation failed, %d\n", ret);
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return ret;
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}
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nvkm_kmap(falcon->core);
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for (i = 0; i < falcon->code.size; i += 4)
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nvkm_wo32(falcon->core, i, falcon->code.data[i / 4]);
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nvkm_done(falcon->core);
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}
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/* upload firmware bootloader (or the full code segments) */
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if (falcon->core) {
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u64 addr = nvkm_memory_addr(falcon->core);
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if (device->card_type < NV_C0)
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nvkm_wr32(device, base + 0x618, 0x04000000);
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else
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nvkm_wr32(device, base + 0x618, 0x00000114);
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nvkm_wr32(device, base + 0x11c, 0);
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nvkm_wr32(device, base + 0x110, addr >> 8);
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nvkm_wr32(device, base + 0x114, 0);
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nvkm_wr32(device, base + 0x118, 0x00006610);
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} else {
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if (falcon->code.size > falcon->code.limit ||
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falcon->data.size > falcon->data.limit) {
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nvkm_error(subdev, "ucode exceeds falcon limit(s)\n");
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return -EINVAL;
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}
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if (falcon->version < 3) {
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nvkm_wr32(device, base + 0xff8, 0x00100000);
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for (i = 0; i < falcon->code.size / 4; i++)
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nvkm_wr32(device, base + 0xff4, falcon->code.data[i]);
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} else {
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nvkm_wr32(device, base + 0x180, 0x01000000);
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for (i = 0; i < falcon->code.size / 4; i++) {
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if ((i & 0x3f) == 0)
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nvkm_wr32(device, base + 0x188, i >> 6);
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nvkm_wr32(device, base + 0x184, falcon->code.data[i]);
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}
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}
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}
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/* upload data segment (if necessary), zeroing the remainder */
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if (falcon->version < 3) {
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nvkm_wr32(device, base + 0xff8, 0x00000000);
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for (i = 0; !falcon->core && i < falcon->data.size / 4; i++)
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nvkm_wr32(device, base + 0xff4, falcon->data.data[i]);
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for (; i < falcon->data.limit; i += 4)
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nvkm_wr32(device, base + 0xff4, 0x00000000);
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} else {
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nvkm_wr32(device, base + 0x1c0, 0x01000000);
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for (i = 0; !falcon->core && i < falcon->data.size / 4; i++)
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nvkm_wr32(device, base + 0x1c4, falcon->data.data[i]);
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for (; i < falcon->data.limit / 4; i++)
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nvkm_wr32(device, base + 0x1c4, 0x00000000);
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}
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/* start it running */
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nvkm_wr32(device, base + 0x10c, 0x00000001); /* BLOCK_ON_FIFO */
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nvkm_wr32(device, base + 0x104, 0x00000000); /* ENTRY */
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nvkm_wr32(device, base + 0x100, 0x00000002); /* TRIGGER */
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nvkm_wr32(device, base + 0x048, 0x00000003); /* FIFO | CHSW */
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if (falcon->func->init)
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falcon->func->init(falcon);
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return 0;
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}
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static void *
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nvkm_falcon_dtor(struct nvkm_engine *engine)
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{
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return nvkm_falcon(engine);
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}
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static const struct nvkm_engine_func
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nvkm_falcon = {
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.dtor = nvkm_falcon_dtor,
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.oneinit = nvkm_falcon_oneinit,
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.init = nvkm_falcon_init,
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.fini = nvkm_falcon_fini,
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.intr = nvkm_falcon_intr,
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.fifo.sclass = nvkm_falcon_oclass_get,
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.cclass = &nvkm_falcon_cclass,
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};
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int
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nvkm_falcon_new_(const struct nvkm_falcon_func *func,
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struct nvkm_device *device, int index, bool enable,
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u32 addr, struct nvkm_engine **pengine)
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{
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struct nvkm_falcon *falcon;
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if (!(falcon = kzalloc(sizeof(*falcon), GFP_KERNEL)))
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return -ENOMEM;
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falcon->func = func;
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falcon->addr = addr;
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falcon->code.data = func->code.data;
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falcon->code.size = func->code.size;
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falcon->data.data = func->data.data;
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falcon->data.size = func->data.size;
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*pengine = &falcon->engine;
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return nvkm_engine_ctor(&nvkm_falcon, device, index,
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enable, &falcon->engine);
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}
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