mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 12:16:41 +07:00
2f02cc3fb8
Signed-off-by: Dave Airlie <airlied@linux.ie>
804 lines
20 KiB
C
804 lines
20 KiB
C
/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
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*/
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/*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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#define IS_I965G(dev) (dev->pci_device == 0x2972 || \
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dev->pci_device == 0x2982 || \
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dev->pci_device == 0x2992 || \
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dev->pci_device == 0x29A2)
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/* Really want an OS-independent resettable timer. Would like to have
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* this loop run for (eg) 3 sec, but have the timer reset every time
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* the head pointer changes, so that EBUSY only happens if the ring
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* actually stalls for (eg) 3 seconds.
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*/
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int i915_wait_ring(drm_device_t * dev, int n, const char *caller)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
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u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
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int i;
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for (i = 0; i < 10000; i++) {
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ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
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ring->space = ring->head - (ring->tail + 8);
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if (ring->space < 0)
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ring->space += ring->Size;
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if (ring->space >= n)
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return 0;
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dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
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if (ring->head != last_head)
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i = 0;
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last_head = ring->head;
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}
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return DRM_ERR(EBUSY);
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}
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void i915_kernel_lost_context(drm_device_t * dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
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ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
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ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
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ring->space = ring->head - (ring->tail + 8);
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if (ring->space < 0)
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ring->space += ring->Size;
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if (ring->head == ring->tail)
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dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
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}
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static int i915_dma_cleanup(drm_device_t * dev)
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{
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/* Make sure interrupts are disabled here because the uninstall ioctl
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* may not have been called from userspace and after dev_private
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* is freed, it's too late.
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*/
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if (dev->irq)
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drm_irq_uninstall(dev);
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if (dev->dev_private) {
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drm_i915_private_t *dev_priv =
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(drm_i915_private_t *) dev->dev_private;
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if (dev_priv->ring.virtual_start) {
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drm_core_ioremapfree(&dev_priv->ring.map, dev);
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}
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if (dev_priv->status_page_dmah) {
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drm_pci_free(dev, dev_priv->status_page_dmah);
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/* Need to rewrite hardware status page */
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I915_WRITE(0x02080, 0x1ffff000);
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}
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drm_free(dev->dev_private, sizeof(drm_i915_private_t),
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DRM_MEM_DRIVER);
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dev->dev_private = NULL;
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}
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return 0;
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}
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static int i915_initialize(drm_device_t * dev,
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drm_i915_private_t * dev_priv,
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drm_i915_init_t * init)
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{
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memset(dev_priv, 0, sizeof(drm_i915_private_t));
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DRM_GETSAREA();
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if (!dev_priv->sarea) {
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DRM_ERROR("can not find sarea!\n");
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dev->dev_private = (void *)dev_priv;
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i915_dma_cleanup(dev);
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return DRM_ERR(EINVAL);
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}
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dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
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if (!dev_priv->mmio_map) {
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dev->dev_private = (void *)dev_priv;
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i915_dma_cleanup(dev);
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DRM_ERROR("can not find mmio map!\n");
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return DRM_ERR(EINVAL);
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}
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dev_priv->sarea_priv = (drm_i915_sarea_t *)
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((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
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dev_priv->ring.Start = init->ring_start;
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dev_priv->ring.End = init->ring_end;
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dev_priv->ring.Size = init->ring_size;
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dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
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dev_priv->ring.map.offset = init->ring_start;
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dev_priv->ring.map.size = init->ring_size;
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dev_priv->ring.map.type = 0;
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dev_priv->ring.map.flags = 0;
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dev_priv->ring.map.mtrr = 0;
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drm_core_ioremap(&dev_priv->ring.map, dev);
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if (dev_priv->ring.map.handle == NULL) {
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dev->dev_private = (void *)dev_priv;
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i915_dma_cleanup(dev);
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DRM_ERROR("can not ioremap virtual address for"
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" ring buffer\n");
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return DRM_ERR(ENOMEM);
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}
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dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
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dev_priv->back_offset = init->back_offset;
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dev_priv->front_offset = init->front_offset;
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dev_priv->current_page = 0;
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dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
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/* We are using separate values as placeholders for mechanisms for
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* private backbuffer/depthbuffer usage.
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*/
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dev_priv->use_mi_batchbuffer_start = 0;
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/* Allow hardware batchbuffers unless told otherwise.
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*/
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dev_priv->allow_batchbuffer = 1;
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/* Program Hardware Status Page */
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dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
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0xffffffff);
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if (!dev_priv->status_page_dmah) {
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dev->dev_private = (void *)dev_priv;
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i915_dma_cleanup(dev);
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DRM_ERROR("Can not allocate hardware status page\n");
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return DRM_ERR(ENOMEM);
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}
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dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
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dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
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memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
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DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
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I915_WRITE(0x02080, dev_priv->dma_status_page);
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DRM_DEBUG("Enabled hardware status page\n");
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dev->dev_private = (void *)dev_priv;
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return 0;
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}
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static int i915_dma_resume(drm_device_t * dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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DRM_DEBUG("%s\n", __FUNCTION__);
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if (!dev_priv->sarea) {
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DRM_ERROR("can not find sarea!\n");
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return DRM_ERR(EINVAL);
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}
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if (!dev_priv->mmio_map) {
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DRM_ERROR("can not find mmio map!\n");
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return DRM_ERR(EINVAL);
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}
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if (dev_priv->ring.map.handle == NULL) {
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DRM_ERROR("can not ioremap virtual address for"
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" ring buffer\n");
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return DRM_ERR(ENOMEM);
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}
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/* Program Hardware Status Page */
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if (!dev_priv->hw_status_page) {
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DRM_ERROR("Can not find hardware status page\n");
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return DRM_ERR(EINVAL);
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}
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DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
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I915_WRITE(0x02080, dev_priv->dma_status_page);
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DRM_DEBUG("Enabled hardware status page\n");
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return 0;
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}
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static int i915_dma_init(DRM_IOCTL_ARGS)
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{
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DRM_DEVICE;
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drm_i915_private_t *dev_priv;
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drm_i915_init_t init;
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int retcode = 0;
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DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data,
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sizeof(init));
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switch (init.func) {
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case I915_INIT_DMA:
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dev_priv = drm_alloc(sizeof(drm_i915_private_t),
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DRM_MEM_DRIVER);
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if (dev_priv == NULL)
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return DRM_ERR(ENOMEM);
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retcode = i915_initialize(dev, dev_priv, &init);
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break;
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case I915_CLEANUP_DMA:
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retcode = i915_dma_cleanup(dev);
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break;
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case I915_RESUME_DMA:
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retcode = i915_dma_resume(dev);
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break;
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default:
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retcode = DRM_ERR(EINVAL);
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break;
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}
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return retcode;
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}
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/* Implement basically the same security restrictions as hardware does
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* for MI_BATCH_NON_SECURE. These can be made stricter at any time.
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*
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* Most of the calculations below involve calculating the size of a
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* particular instruction. It's important to get the size right as
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* that tells us where the next instruction to check is. Any illegal
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* instruction detected will be given a size of zero, which is a
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* signal to abort the rest of the buffer.
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*/
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static int do_validate_cmd(int cmd)
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{
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switch (((cmd >> 29) & 0x7)) {
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case 0x0:
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switch ((cmd >> 23) & 0x3f) {
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case 0x0:
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return 1; /* MI_NOOP */
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case 0x4:
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return 1; /* MI_FLUSH */
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default:
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return 0; /* disallow everything else */
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}
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break;
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case 0x1:
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return 0; /* reserved */
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case 0x2:
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return (cmd & 0xff) + 2; /* 2d commands */
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case 0x3:
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if (((cmd >> 24) & 0x1f) <= 0x18)
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return 1;
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switch ((cmd >> 24) & 0x1f) {
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case 0x1c:
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return 1;
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case 0x1d:
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switch ((cmd >> 16) & 0xff) {
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case 0x3:
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return (cmd & 0x1f) + 2;
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case 0x4:
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return (cmd & 0xf) + 2;
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default:
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return (cmd & 0xffff) + 2;
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}
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case 0x1e:
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if (cmd & (1 << 23))
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return (cmd & 0xffff) + 1;
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else
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return 1;
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case 0x1f:
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if ((cmd & (1 << 23)) == 0) /* inline vertices */
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return (cmd & 0x1ffff) + 2;
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else if (cmd & (1 << 17)) /* indirect random */
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if ((cmd & 0xffff) == 0)
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return 0; /* unknown length, too hard */
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else
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return (((cmd & 0xffff) + 1) / 2) + 1;
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else
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return 2; /* indirect sequential */
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default:
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return 0;
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}
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default:
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return 0;
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}
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return 0;
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}
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static int validate_cmd(int cmd)
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{
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int ret = do_validate_cmd(cmd);
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/* printk("validate_cmd( %x ): %d\n", cmd, ret); */
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return ret;
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}
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static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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int i;
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RING_LOCALS;
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if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
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return DRM_ERR(EINVAL);
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BEGIN_LP_RING((dwords+1)&~1);
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for (i = 0; i < dwords;) {
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int cmd, sz;
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if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
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return DRM_ERR(EINVAL);
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if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
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return DRM_ERR(EINVAL);
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OUT_RING(cmd);
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while (++i, --sz) {
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if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
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sizeof(cmd))) {
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return DRM_ERR(EINVAL);
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}
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OUT_RING(cmd);
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}
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}
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if (dwords & 1)
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OUT_RING(0);
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ADVANCE_LP_RING();
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return 0;
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}
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static int i915_emit_box(drm_device_t * dev,
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drm_clip_rect_t __user * boxes,
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int i, int DR1, int DR4)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_clip_rect_t box;
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RING_LOCALS;
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if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
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return DRM_ERR(EFAULT);
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}
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if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
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DRM_ERROR("Bad box %d,%d..%d,%d\n",
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box.x1, box.y1, box.x2, box.y2);
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return DRM_ERR(EINVAL);
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}
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if (IS_I965G(dev)) {
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BEGIN_LP_RING(4);
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OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
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OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
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OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
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OUT_RING(DR4);
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ADVANCE_LP_RING();
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} else {
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BEGIN_LP_RING(6);
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OUT_RING(GFX_OP_DRAWRECT_INFO);
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OUT_RING(DR1);
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OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
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OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
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OUT_RING(DR4);
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OUT_RING(0);
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ADVANCE_LP_RING();
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}
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return 0;
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}
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/* XXX: Emitting the counter should really be moved to part of the IRQ
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* emit. For now, do it in both places:
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*/
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static void i915_emit_breadcrumb(drm_device_t *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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RING_LOCALS;
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dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
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if (dev_priv->counter > 0x7FFFFFFFUL)
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dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
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BEGIN_LP_RING(4);
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OUT_RING(CMD_STORE_DWORD_IDX);
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OUT_RING(20);
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OUT_RING(dev_priv->counter);
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OUT_RING(0);
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ADVANCE_LP_RING();
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}
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static int i915_dispatch_cmdbuffer(drm_device_t * dev,
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drm_i915_cmdbuffer_t * cmd)
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{
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int nbox = cmd->num_cliprects;
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int i = 0, count, ret;
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if (cmd->sz & 0x3) {
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DRM_ERROR("alignment");
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return DRM_ERR(EINVAL);
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}
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i915_kernel_lost_context(dev);
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count = nbox ? nbox : 1;
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for (i = 0; i < count; i++) {
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if (i < nbox) {
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ret = i915_emit_box(dev, cmd->cliprects, i,
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cmd->DR1, cmd->DR4);
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if (ret)
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return ret;
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}
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ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
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if (ret)
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return ret;
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}
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i915_emit_breadcrumb(dev);
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return 0;
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}
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static int i915_dispatch_batchbuffer(drm_device_t * dev,
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drm_i915_batchbuffer_t * batch)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_clip_rect_t __user *boxes = batch->cliprects;
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int nbox = batch->num_cliprects;
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int i = 0, count;
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RING_LOCALS;
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if ((batch->start | batch->used) & 0x7) {
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DRM_ERROR("alignment");
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return DRM_ERR(EINVAL);
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}
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i915_kernel_lost_context(dev);
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count = nbox ? nbox : 1;
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for (i = 0; i < count; i++) {
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if (i < nbox) {
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int ret = i915_emit_box(dev, boxes, i,
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batch->DR1, batch->DR4);
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if (ret)
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return ret;
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}
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if (dev_priv->use_mi_batchbuffer_start) {
|
|
BEGIN_LP_RING(2);
|
|
OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
|
|
OUT_RING(batch->start | MI_BATCH_NON_SECURE);
|
|
ADVANCE_LP_RING();
|
|
} else {
|
|
BEGIN_LP_RING(4);
|
|
OUT_RING(MI_BATCH_BUFFER);
|
|
OUT_RING(batch->start | MI_BATCH_NON_SECURE);
|
|
OUT_RING(batch->start + batch->used - 4);
|
|
OUT_RING(0);
|
|
ADVANCE_LP_RING();
|
|
}
|
|
}
|
|
|
|
i915_emit_breadcrumb(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i915_dispatch_flip(drm_device_t * dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
RING_LOCALS;
|
|
|
|
DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
|
|
__FUNCTION__,
|
|
dev_priv->current_page,
|
|
dev_priv->sarea_priv->pf_current_page);
|
|
|
|
i915_kernel_lost_context(dev);
|
|
|
|
BEGIN_LP_RING(2);
|
|
OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
|
|
OUT_RING(0);
|
|
ADVANCE_LP_RING();
|
|
|
|
BEGIN_LP_RING(6);
|
|
OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
|
|
OUT_RING(0);
|
|
if (dev_priv->current_page == 0) {
|
|
OUT_RING(dev_priv->back_offset);
|
|
dev_priv->current_page = 1;
|
|
} else {
|
|
OUT_RING(dev_priv->front_offset);
|
|
dev_priv->current_page = 0;
|
|
}
|
|
OUT_RING(0);
|
|
ADVANCE_LP_RING();
|
|
|
|
BEGIN_LP_RING(2);
|
|
OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
|
|
OUT_RING(0);
|
|
ADVANCE_LP_RING();
|
|
|
|
dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
|
|
|
|
BEGIN_LP_RING(4);
|
|
OUT_RING(CMD_STORE_DWORD_IDX);
|
|
OUT_RING(20);
|
|
OUT_RING(dev_priv->counter);
|
|
OUT_RING(0);
|
|
ADVANCE_LP_RING();
|
|
|
|
dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
|
|
return 0;
|
|
}
|
|
|
|
static int i915_quiescent(drm_device_t * dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
i915_kernel_lost_context(dev);
|
|
return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
|
|
}
|
|
|
|
static int i915_flush_ioctl(DRM_IOCTL_ARGS)
|
|
{
|
|
DRM_DEVICE;
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
|
|
|
return i915_quiescent(dev);
|
|
}
|
|
|
|
static int i915_batchbuffer(DRM_IOCTL_ARGS)
|
|
{
|
|
DRM_DEVICE;
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
u32 *hw_status = dev_priv->hw_status_page;
|
|
drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
|
|
dev_priv->sarea_priv;
|
|
drm_i915_batchbuffer_t batch;
|
|
int ret;
|
|
|
|
if (!dev_priv->allow_batchbuffer) {
|
|
DRM_ERROR("Batchbuffer ioctl disabled\n");
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
|
|
DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data,
|
|
sizeof(batch));
|
|
|
|
DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
|
|
batch.start, batch.used, batch.num_cliprects);
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
|
|
|
if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
|
|
batch.num_cliprects *
|
|
sizeof(drm_clip_rect_t)))
|
|
return DRM_ERR(EFAULT);
|
|
|
|
ret = i915_dispatch_batchbuffer(dev, &batch);
|
|
|
|
sarea_priv->last_dispatch = (int)hw_status[5];
|
|
return ret;
|
|
}
|
|
|
|
static int i915_cmdbuffer(DRM_IOCTL_ARGS)
|
|
{
|
|
DRM_DEVICE;
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
u32 *hw_status = dev_priv->hw_status_page;
|
|
drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
|
|
dev_priv->sarea_priv;
|
|
drm_i915_cmdbuffer_t cmdbuf;
|
|
int ret;
|
|
|
|
DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data,
|
|
sizeof(cmdbuf));
|
|
|
|
DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
|
|
cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
|
|
|
if (cmdbuf.num_cliprects &&
|
|
DRM_VERIFYAREA_READ(cmdbuf.cliprects,
|
|
cmdbuf.num_cliprects *
|
|
sizeof(drm_clip_rect_t))) {
|
|
DRM_ERROR("Fault accessing cliprects\n");
|
|
return DRM_ERR(EFAULT);
|
|
}
|
|
|
|
ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
|
|
if (ret) {
|
|
DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
|
|
return ret;
|
|
}
|
|
|
|
sarea_priv->last_dispatch = (int)hw_status[5];
|
|
return 0;
|
|
}
|
|
|
|
static int i915_flip_bufs(DRM_IOCTL_ARGS)
|
|
{
|
|
DRM_DEVICE;
|
|
|
|
DRM_DEBUG("%s\n", __FUNCTION__);
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, filp);
|
|
|
|
return i915_dispatch_flip(dev);
|
|
}
|
|
|
|
static int i915_getparam(DRM_IOCTL_ARGS)
|
|
{
|
|
DRM_DEVICE;
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
drm_i915_getparam_t param;
|
|
int value;
|
|
|
|
if (!dev_priv) {
|
|
DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
|
|
DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data,
|
|
sizeof(param));
|
|
|
|
switch (param.param) {
|
|
case I915_PARAM_IRQ_ACTIVE:
|
|
value = dev->irq ? 1 : 0;
|
|
break;
|
|
case I915_PARAM_ALLOW_BATCHBUFFER:
|
|
value = dev_priv->allow_batchbuffer ? 1 : 0;
|
|
break;
|
|
case I915_PARAM_LAST_DISPATCH:
|
|
value = READ_BREADCRUMB(dev_priv);
|
|
break;
|
|
default:
|
|
DRM_ERROR("Unknown parameter %d\n", param.param);
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
|
|
if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
|
|
DRM_ERROR("DRM_COPY_TO_USER failed\n");
|
|
return DRM_ERR(EFAULT);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i915_setparam(DRM_IOCTL_ARGS)
|
|
{
|
|
DRM_DEVICE;
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
drm_i915_setparam_t param;
|
|
|
|
if (!dev_priv) {
|
|
DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
|
|
DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data,
|
|
sizeof(param));
|
|
|
|
switch (param.param) {
|
|
case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
|
|
dev_priv->use_mi_batchbuffer_start = param.value;
|
|
break;
|
|
case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
|
|
dev_priv->tex_lru_log_granularity = param.value;
|
|
break;
|
|
case I915_SETPARAM_ALLOW_BATCHBUFFER:
|
|
dev_priv->allow_batchbuffer = param.value;
|
|
break;
|
|
default:
|
|
DRM_ERROR("unknown parameter %d\n", param.param);
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int i915_driver_load(drm_device_t *dev, unsigned long flags)
|
|
{
|
|
/* i915 has 4 more counters */
|
|
dev->counters += 4;
|
|
dev->types[6] = _DRM_STAT_IRQ;
|
|
dev->types[7] = _DRM_STAT_PRIMARY;
|
|
dev->types[8] = _DRM_STAT_SECONDARY;
|
|
dev->types[9] = _DRM_STAT_DMA;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void i915_driver_lastclose(drm_device_t * dev)
|
|
{
|
|
if (dev->dev_private) {
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
i915_mem_takedown(&(dev_priv->agp_heap));
|
|
}
|
|
i915_dma_cleanup(dev);
|
|
}
|
|
|
|
void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
|
|
{
|
|
if (dev->dev_private) {
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
i915_mem_release(dev, filp, dev_priv->agp_heap);
|
|
}
|
|
}
|
|
|
|
drm_ioctl_desc_t i915_ioctls[] = {
|
|
[DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
|
|
[DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH},
|
|
[DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH},
|
|
[DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, DRM_AUTH},
|
|
[DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, DRM_AUTH},
|
|
[DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, DRM_AUTH},
|
|
[DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, DRM_AUTH},
|
|
[DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
|
|
[DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, DRM_AUTH},
|
|
[DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH},
|
|
[DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
|
|
[DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH},
|
|
[DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
|
|
[DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
|
|
[DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
|
|
};
|
|
|
|
int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
|
|
|
|
/**
|
|
* Determine if the device really is AGP or not.
|
|
*
|
|
* All Intel graphics chipsets are treated as AGP, even if they are really
|
|
* PCI-e.
|
|
*
|
|
* \param dev The device to be tested.
|
|
*
|
|
* \returns
|
|
* A value of 1 is always retured to indictate every i9x5 is AGP.
|
|
*/
|
|
int i915_driver_device_is_agp(drm_device_t * dev)
|
|
{
|
|
return 1;
|
|
}
|